Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 2 | |
Patrick Georgi | 334328a | 2012-02-16 19:01:22 +0100 | [diff] [blame] | 3 | #include "hostbridge.asl" |
| 4 | #include "../i945.h" |
Elyes HAOUAS | 4ec67fc | 2019-10-30 12:39:17 +0100 | [diff] [blame] | 5 | #include <southbridge/intel/common/rcba.h> |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 6 | |
Denis 'GNUtoo' Carikli | 4b213a8 | 2013-03-28 14:24:39 +0100 | [diff] [blame] | 7 | /* Operating System Capabilities Method */ |
| 8 | Method (_OSC, 4) |
| 9 | { |
Denis 'GNUtoo' Carikli | 4b213a8 | 2013-03-28 14:24:39 +0100 | [diff] [blame] | 10 | /* Check for proper PCI/PCIe UUID */ |
Elyes HAOUAS | e298391 | 2020-09-10 20:36:14 +0200 | [diff] [blame] | 11 | If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) |
Denis 'GNUtoo' Carikli | 4b213a8 | 2013-03-28 14:24:39 +0100 | [diff] [blame] | 12 | { |
| 13 | /* Let OS control everything */ |
| 14 | Return(Arg3) |
| 15 | } Else { |
Marc Jones | 1faa11e | 2018-08-15 22:17:45 -0600 | [diff] [blame] | 16 | CreateDWordField(Arg3, 0, CDW1) |
Elyes HAOUAS | e298391 | 2020-09-10 20:36:14 +0200 | [diff] [blame] | 17 | CDW1 = CDW1 | 4 // Unrecognized UUID, so set bit 2 to 1 |
Denis 'GNUtoo' Carikli | 4b213a8 | 2013-03-28 14:24:39 +0100 | [diff] [blame] | 18 | Return(Arg3) |
| 19 | } |
| 20 | } |
| 21 | |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 22 | /* PCI Device Resource Consumption */ |
| 23 | Device (PDRC) |
| 24 | { |
| 25 | Name (_HID, EISAID("PNP0C02")) |
| 26 | Name (_UID, 1) |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 27 | |
| 28 | // This does not seem to work correctly yet - set values statically for |
| 29 | // now. |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 30 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 31 | //Name (PDRS, ResourceTemplate() { |
| 32 | // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA |
| 33 | // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR |
| 34 | // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR |
| 35 | // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR |
| 36 | // Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR |
| 37 | // Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH |
| 38 | //}) |
| 39 | |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 40 | Name (PDRS, ResourceTemplate() { |
Elyes HAOUAS | 4ec67fc | 2019-10-30 12:39:17 +0100 | [diff] [blame] | 41 | Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 42 | Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) |
| 43 | Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) |
| 44 | Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) |
Angel Pons | a6b0922 | 2021-01-20 13:00:02 +0100 | [diff] [blame^] | 45 | Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 46 | Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH |
| 47 | Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH |
| 48 | Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 49 | }) |
| 50 | |
| 51 | // Current Resource Settings |
| 52 | Method (_CRS, 0, Serialized) |
| 53 | { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 54 | //CreateDwordField(PDRS, ^RCRB._BAS, RBR0) |
Elyes HAOUAS | e298391 | 2020-09-10 20:36:14 +0200 | [diff] [blame] | 55 | //RBR0 = \_SB.PCI0.LPCB.RCBA << 14 |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 56 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 57 | //CreateDwordField(PDRS, ^MCHB._BAS, MBR0) |
Elyes HAOUAS | e298391 | 2020-09-10 20:36:14 +0200 | [diff] [blame] | 58 | //MBR0 = \_SB.PCI0.MCHC.MHBR << 14 |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 59 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 60 | //CreateDwordField(PDRS, ^DMIB._BAS, DBR0) |
Elyes HAOUAS | e298391 | 2020-09-10 20:36:14 +0200 | [diff] [blame] | 61 | //DBR0 = \_SB.PCI0.MCHC.DMBR << 12 |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 62 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 63 | //CreateDwordField(PDRS, ^EGPB._BAS, EBR0) |
Elyes HAOUAS | e298391 | 2020-09-10 20:36:14 +0200 | [diff] [blame] | 64 | //EBR0 = \_SB.PCI0.MCHC.EPBR << 12 |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 65 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 66 | //CreateDwordField(PDRS, ^PCIE._BAS, PBR0) |
Elyes HAOUAS | e298391 | 2020-09-10 20:36:14 +0200 | [diff] [blame] | 67 | //PBR0 = \_SB.PCI0.MCHC.PXBR << 26 |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 68 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 69 | //CreateDwordField(PDRS, ^PCIE._LEN, PSZ0) |
Elyes HAOUAS | e298391 | 2020-09-10 20:36:14 +0200 | [diff] [blame] | 70 | //PSZ0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 71 | |
| 72 | Return(PDRS) |
| 73 | } |
| 74 | } |
| 75 | |
| 76 | // PCIe graphics port 0:1.0 |
Patrick Georgi | 334328a | 2012-02-16 19:01:22 +0100 | [diff] [blame] | 77 | #include "peg.asl" |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 78 | |
| 79 | // Integrated graphics 0:2.0 |
Matt DeVillier | c6589ae | 2020-11-28 13:17:54 -0600 | [diff] [blame] | 80 | #include <drivers/intel/gma/acpi/gfx.asl> |
Patrick Georgi | 334328a | 2012-02-16 19:01:22 +0100 | [diff] [blame] | 81 | #include "igd.asl" |