Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 3 | |
Patrick Georgi | 334328a | 2012-02-16 19:01:22 +0100 | [diff] [blame] | 4 | #include "hostbridge.asl" |
| 5 | #include "../i945.h" |
Elyes HAOUAS | 4ec67fc | 2019-10-30 12:39:17 +0100 | [diff] [blame] | 6 | #include <southbridge/intel/common/rcba.h> |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 7 | |
Denis 'GNUtoo' Carikli | 4b213a8 | 2013-03-28 14:24:39 +0100 | [diff] [blame] | 8 | /* Operating System Capabilities Method */ |
| 9 | Method (_OSC, 4) |
| 10 | { |
Denis 'GNUtoo' Carikli | 4b213a8 | 2013-03-28 14:24:39 +0100 | [diff] [blame] | 11 | /* Check for proper PCI/PCIe UUID */ |
| 12 | If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) |
| 13 | { |
| 14 | /* Let OS control everything */ |
| 15 | Return(Arg3) |
| 16 | } Else { |
Marc Jones | 1faa11e | 2018-08-15 22:17:45 -0600 | [diff] [blame] | 17 | CreateDWordField(Arg3, 0, CDW1) |
Denis 'GNUtoo' Carikli | 4b213a8 | 2013-03-28 14:24:39 +0100 | [diff] [blame] | 18 | Or(CDW1, 4, CDW1) // Unrecognized UUID, so set bit 2 to 1 |
| 19 | Return(Arg3) |
| 20 | } |
| 21 | } |
| 22 | |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 23 | /* PCI Device Resource Consumption */ |
| 24 | Device (PDRC) |
| 25 | { |
| 26 | Name (_HID, EISAID("PNP0C02")) |
| 27 | Name (_UID, 1) |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 28 | |
| 29 | // This does not seem to work correctly yet - set values statically for |
| 30 | // now. |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 31 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 32 | //Name (PDRS, ResourceTemplate() { |
| 33 | // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA |
| 34 | // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR |
| 35 | // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR |
| 36 | // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR |
| 37 | // Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR |
| 38 | // Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH |
| 39 | //}) |
| 40 | |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 41 | Name (PDRS, ResourceTemplate() { |
Elyes HAOUAS | 4ec67fc | 2019-10-30 12:39:17 +0100 | [diff] [blame] | 42 | Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame^] | 43 | Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) |
| 44 | Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) |
| 45 | Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) |
Kyösti Mälkki | 503d324 | 2019-03-05 07:54:28 +0200 | [diff] [blame] | 46 | Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 47 | Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH |
| 48 | Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH |
| 49 | Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 50 | }) |
| 51 | |
| 52 | // Current Resource Settings |
| 53 | Method (_CRS, 0, Serialized) |
| 54 | { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 55 | //CreateDwordField(PDRS, ^RCRB._BAS, RBR0) |
| 56 | //ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0) |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 57 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 58 | //CreateDwordField(PDRS, ^MCHB._BAS, MBR0) |
| 59 | //ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0) |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 60 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 61 | //CreateDwordField(PDRS, ^DMIB._BAS, DBR0) |
| 62 | //ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0) |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 63 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 64 | //CreateDwordField(PDRS, ^EGPB._BAS, EBR0) |
| 65 | //ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0) |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 66 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 67 | //CreateDwordField(PDRS, ^PCIE._BAS, PBR0) |
| 68 | //ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0) |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 69 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 70 | //CreateDwordField(PDRS, ^PCIE._LEN, PSZ0) |
| 71 | //ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0) |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 72 | |
| 73 | Return(PDRS) |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | // PCIe graphics port 0:1.0 |
Patrick Georgi | 334328a | 2012-02-16 19:01:22 +0100 | [diff] [blame] | 78 | #include "peg.asl" |
Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 79 | |
| 80 | // Integrated graphics 0:2.0 |
Patrick Georgi | 334328a | 2012-02-16 19:01:22 +0100 | [diff] [blame] | 81 | #include "igd.asl" |