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review.coreboot.org / coreboot / a5215c4eb3a4cbe0ef32257c4da2e5a6e0febdef / . / src / soc / intel / cannonlake / acpi / xhci.asl
blob: beaa843911278ae471f9b628295e6a2cfb06ef17 [file] [log] [blame]
Angel Ponsf5627e82020-04-05 15:46:52 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Lijian Zhaoae565462017-10-02 19:18:16 -0700[diff] [blame]2
Subrata Banik36ca7b32023-03-23 14:48:53 +0530[diff] [blame]3#include <intelblocks/xhci.h>
Lijian Zhaoae565462017-10-02 19:18:16 -0700[diff] [blame]4#include <soc/gpe.h>
Lijian Zhaoae565462017-10-02 19:18:16 -0700[diff] [blame]5
Reka Normana5215c42023-09-22 15:26:54 +1000[diff] [blame^]6/* Include UWES method for enabling USB wake */
7#include <soc/intel/common/acpi/xhci_wake.asl>
Edward O'Callaghan81128412020-06-24 09:45:49 +1000[diff] [blame]8
Lijian Zhaoae565462017-10-02 19:18:16 -0700[diff] [blame]9/* XHCI Controller 0:14.0 */
10
11Device (XHCI)
12{
13 Name (_ADR, 0x00140000)
14
Patrick Rudolph7c8de862021-01-07 16:47:23 +0100[diff] [blame]15 Name (_PRW, Package () { GPE0_PME_B0, 4 })
Lijian Zhaoae565462017-10-02 19:18:16 -0700[diff] [blame]16
Edward O'Callaghan81128412020-06-24 09:45:49 +1000[diff] [blame]17 Method (_DSW, 3)
18 {
19 UWES ((\U2WE & 0xFFF), PORTSCN_OFFSET, XMEM)
20 UWES ((\U3WE & 0x3F ), PORTSCXUSB3_OFFSET, XMEM)
21 }
22
Lijian Zhaoae565462017-10-02 19:18:16 -0700[diff] [blame]23 Name (_S3D, 3) /* D3 supported in S3 */
Lijian Zhaoae565462017-10-02 19:18:16 -0700[diff] [blame]24 Name (_S0W, 3) /* D3 can wake device in S0 */
25 Name (_S3W, 3) /* D3 can wake system from S3 */
Lijian Zhaoae565462017-10-02 19:18:16 -0700[diff] [blame]26
Patrick Rudolph7c8de862021-01-07 16:47:23 +0100[diff] [blame]27 Name (_S4D, 3) /* D3 supported in S4 */
28 Name (_S4W, 3) /* D3 can wake system from S4 */
29
Edward O'Callaghan81128412020-06-24 09:45:49 +1000[diff] [blame]30 OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
31 Field (XPRT, AnyAcc, NoLock, Preserve)
32 {
33 Offset (0x10),
34 , 16,
35 XMEM, 16, /* MEM_BASE */
Angel Pons05df1082023-02-08 21:33:44 +0100[diff] [blame]36 Offset (0x74),
37 D0D3, 2, /* POWERSTATE */
38 , 6,
39 PMEE, 1, /* PME_EN */
40 , 6,
41 PMES, 1, /* PME_STS */
Edward O'Callaghan81128412020-06-24 09:45:49 +1000[diff] [blame]42 }
43
Lijian Zhaoae565462017-10-02 19:18:16 -0700[diff] [blame]44 Method (_PS0, 0, Serialized)
45 {
Lijian Zhaoae565462017-10-02 19:18:16 -0700[diff] [blame]46
Lijian Zhaoae565462017-10-02 19:18:16 -0700[diff] [blame]47 }
48
49 Method (_PS3, 0, Serialized)
50 {
Lijian Zhaoae565462017-10-02 19:18:16 -0700[diff] [blame]51
Lijian Zhaoae565462017-10-02 19:18:16 -0700[diff] [blame]52 }
53
54 /* Root Hub for Cannonlake-LP PCH */
55 Device (RHUB)
56 {
Felix Singer9df60d32022-12-26 09:43:07 +0100[diff] [blame]57 Name (_ADR, 0)
Lijian Zhaoae565462017-10-02 19:18:16 -0700[diff] [blame]58
59 /* USB2 */
60 Device (HS01) { Name (_ADR, 1) }
61 Device (HS02) { Name (_ADR, 2) }
62 Device (HS03) { Name (_ADR, 3) }
63 Device (HS04) { Name (_ADR, 4) }
64 Device (HS05) { Name (_ADR, 5) }
65 Device (HS06) { Name (_ADR, 6) }
66 Device (HS07) { Name (_ADR, 7) }
67 Device (HS08) { Name (_ADR, 8) }
68 Device (HS09) { Name (_ADR, 9) }
69 Device (HS10) { Name (_ADR, 10) }
70 Device (HS11) { Name (_ADR, 11) }
71 Device (HS12) { Name (_ADR, 12) }
72
73 /* USBr */
74 Device (USR1) { Name (_ADR, 11) }
75 Device (USR2) { Name (_ADR, 12) }
76
77 /* USB3 */
78 Device (SS01) { Name (_ADR, 13) }
79 Device (SS02) { Name (_ADR, 14) }
80 Device (SS03) { Name (_ADR, 15) }
81 Device (SS04) { Name (_ADR, 16) }
82 Device (SS05) { Name (_ADR, 17) }
83 Device (SS06) { Name (_ADR, 18) }
84 }
85}