Lijian Zhao | ae56546 | 2017-10-02 19:18:16 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2015 Google Inc. |
| 6 | * Copyright (C) 2015 Intel Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <soc/gpe.h> |
| 19 | /* |
| 20 | * USB Port Wake Enable (UPWE) on usb attach/detach |
| 21 | * Arg0 - Port Number |
| 22 | * Arg1 - Port 1 Status and control offset |
| 23 | * Arg2 - xHCI Memory-mapped address |
| 24 | */ |
| 25 | Method (UPWE, 3, Serialized) |
| 26 | { |
| 27 | /* Local0 = Arg1 + ((Arg0 - 1) * 0x10) */ |
| 28 | Add (Arg1, Multiply (Subtract (Arg0, 1), 0x10), Local0) |
| 29 | |
| 30 | /* Map ((XMEM << 16) + Local0 in PSCR */ |
| 31 | OperationRegion (PSCR, SystemMemory, |
| 32 | Add (ShiftLeft (Arg2, 16), Local0), 0x10) |
| 33 | Field (PSCR, AnyAcc, NoLock, Preserve) |
| 34 | { |
| 35 | , 25, |
| 36 | UPCE, 1, |
| 37 | UPDE, 1, |
| 38 | } |
| 39 | Store (One, UPCE) |
| 40 | Store (One, UPDE) |
| 41 | } |
| 42 | |
| 43 | /* |
| 44 | * USB Wake Enable Setup (UWES) |
| 45 | * Arg0 - Port enable bitmap |
| 46 | * Arg1 - Port 1 Status and control offset |
| 47 | * Arg2 - xHCI Memory-mapped address |
| 48 | */ |
| 49 | Method (UWES, 3, Serialized) |
| 50 | { |
| 51 | Store (Arg0, Local0) |
| 52 | |
| 53 | While (One) { |
| 54 | FindSetRightBit (Local0, Local1) |
| 55 | If (LEqual (Local1, Zero)) { |
| 56 | Break |
| 57 | } |
| 58 | UPWE (Local1, Arg1, Arg2) |
| 59 | /* |
| 60 | * Clear the lowest set bit in Local0 since it was |
| 61 | * processed. |
| 62 | * Local0 = Local0 & (Local0 - 1) |
| 63 | */ |
| 64 | And (Local0, Subtract (Local0, 1), Local0) |
| 65 | } |
| 66 | } |
| 67 | |
| 68 | /* XHCI Controller 0:14.0 */ |
| 69 | |
| 70 | Device (XHCI) |
| 71 | { |
| 72 | Name (_ADR, 0x00140000) |
| 73 | |
| 74 | Name (_PRW, Package () { GPE0_PME_B0, 3 }) |
| 75 | |
| 76 | Method (_DSW, 3) |
| 77 | { |
| 78 | Store (Arg0, PMEE) |
| 79 | UWES (And (\U2WE, 0x3FF), 0x480, XMEM) |
| 80 | UWES (And (\U3WE, 0x3F), 0x540, XMEM) |
| 81 | } |
| 82 | |
| 83 | Name (_S3D, 3) /* D3 supported in S3 */ |
| 84 | Name (_S4D, 3) /* D3 supported in S4 */ |
| 85 | Name (_S0W, 3) /* D3 can wake device in S0 */ |
| 86 | Name (_S3W, 3) /* D3 can wake system from S3 */ |
| 87 | Name (_S4W, 3) /* D3 can wake system from S4 */ |
| 88 | |
| 89 | OperationRegion (XPRT, PCI_Config, 0x00, 0x100) |
| 90 | Field (XPRT, AnyAcc, NoLock, Preserve) |
| 91 | { |
| 92 | Offset (0x0), |
| 93 | DVID, 16, /* VENDORID */ |
| 94 | Offset (0x10), |
| 95 | , 16, |
| 96 | XMEM, 16, /* MEM_BASE */ |
| 97 | Offset (0x50), /* XHCLKGTEN */ |
| 98 | , 2, |
| 99 | STGE, 1, /* SS Link Trunk clock gating enable */ |
| 100 | Offset (0x74), |
| 101 | D0D3, 2, /* POWERSTATE */ |
| 102 | , 6, |
| 103 | PMEE, 1, /* PME_EN */ |
| 104 | , 6, |
| 105 | PMES, 1, /* PME_STS */ |
| 106 | Offset (0xA2), |
| 107 | , 2, |
| 108 | D3HE, 1, /* D3_hot_en */ |
| 109 | } |
| 110 | |
| 111 | OperationRegion (XREG, SystemMemory, |
| 112 | Add (ShiftLeft (XMEM, 16), 0x8000), 0x200) |
| 113 | Field (XREG, DWordAcc, Lock, Preserve) |
| 114 | { |
| 115 | Offset (0x1c4), /* USB2PMCTRL */ |
| 116 | , 2, |
| 117 | UPSW, 2, /* U2PSUSPGP */ |
| 118 | } |
| 119 | |
| 120 | Method (_PSC, 0, Serialized) |
| 121 | { |
| 122 | Return (^D0D3) |
| 123 | } |
| 124 | |
| 125 | Method (_PS0, 0, Serialized) |
| 126 | { |
| 127 | If (LEqual (^DVID, 0xFFFF)) { |
| 128 | Return |
| 129 | } |
| 130 | If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { |
| 131 | Return |
| 132 | } |
| 133 | |
| 134 | /* Disable d3hot and SS link trunk clock gating */ |
| 135 | Store(Zero, ^D3HE) |
| 136 | Store(Zero, ^STGE) |
| 137 | |
| 138 | /* If device is in D3, set back to D0 */ |
| 139 | If (LEqual (^D0D3, 3)) { |
| 140 | Store (Zero, Local0) |
| 141 | Store (Local0, ^D0D3) |
| 142 | Store (^D0D3, Local0) |
| 143 | } |
| 144 | |
| 145 | /* Disable USB2 PHY SUS Well Power Gating */ |
| 146 | Store (Zero, ^UPSW) |
| 147 | } |
| 148 | |
| 149 | Method (_PS3, 0, Serialized) |
| 150 | { |
| 151 | If (LEqual (^DVID, 0xFFFF)) { |
| 152 | Return |
| 153 | } |
| 154 | If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { |
| 155 | Return |
| 156 | } |
| 157 | |
| 158 | /* Clear PME Status */ |
| 159 | Store (1, ^PMES) |
| 160 | |
| 161 | /* Enable PME */ |
| 162 | Store (1, ^PMEE) |
| 163 | |
| 164 | /* If device is in D3, set back to D0 */ |
| 165 | If (LEqual (^D0D3, 3)) { |
| 166 | Store (Zero, Local0) |
| 167 | Store (Local0, ^D0D3) |
| 168 | Store (^D0D3, Local0) |
| 169 | } |
| 170 | |
| 171 | /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ |
| 172 | Store (3, ^UPSW) |
| 173 | |
| 174 | /* Enable d3hot and SS link trunk clock gating */ |
| 175 | Store(One, ^D3HE) |
| 176 | Store(One, ^STGE) |
| 177 | |
| 178 | /* Now put device in D3 */ |
| 179 | Store (3, Local0) |
| 180 | Store (Local0, ^D0D3) |
| 181 | Store (^D0D3, Local0) |
| 182 | } |
| 183 | |
| 184 | /* Root Hub for Cannonlake-LP PCH */ |
| 185 | Device (RHUB) |
| 186 | { |
| 187 | Name (_ADR, Zero) |
| 188 | |
| 189 | /* USB2 */ |
| 190 | Device (HS01) { Name (_ADR, 1) } |
| 191 | Device (HS02) { Name (_ADR, 2) } |
| 192 | Device (HS03) { Name (_ADR, 3) } |
| 193 | Device (HS04) { Name (_ADR, 4) } |
| 194 | Device (HS05) { Name (_ADR, 5) } |
| 195 | Device (HS06) { Name (_ADR, 6) } |
| 196 | Device (HS07) { Name (_ADR, 7) } |
| 197 | Device (HS08) { Name (_ADR, 8) } |
| 198 | Device (HS09) { Name (_ADR, 9) } |
| 199 | Device (HS10) { Name (_ADR, 10) } |
| 200 | Device (HS11) { Name (_ADR, 11) } |
| 201 | Device (HS12) { Name (_ADR, 12) } |
| 202 | |
| 203 | /* USBr */ |
| 204 | Device (USR1) { Name (_ADR, 11) } |
| 205 | Device (USR2) { Name (_ADR, 12) } |
| 206 | |
| 207 | /* USB3 */ |
| 208 | Device (SS01) { Name (_ADR, 13) } |
| 209 | Device (SS02) { Name (_ADR, 14) } |
| 210 | Device (SS03) { Name (_ADR, 15) } |
| 211 | Device (SS04) { Name (_ADR, 16) } |
| 212 | Device (SS05) { Name (_ADR, 17) } |
| 213 | Device (SS06) { Name (_ADR, 18) } |
| 214 | } |
| 215 | } |