soc/intel/cannonlake: Add UWES ASL into xhci.asl
Align support for enable wake-on-usb attach/detach as was
introduced in Skylake in
`commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`.
This adds the USB Wake Enable Setup (UWES) ASL blocks
required to inform the OS about plug wake events bits
being set in the PORTSCN register configured by devicetree.
BUG=b:159187889
BRANCH=none
TEST=none
Change-Id: I6c63d226e5acadff04486c8a6764fb715a0ac051
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl
index d5187e6..7d89665 100644
--- a/src/soc/intel/cannonlake/acpi/xhci.asl
+++ b/src/soc/intel/cannonlake/acpi/xhci.asl
@@ -2,6 +2,65 @@
#include <soc/gpe.h>
+#define PORTSCN_OFFSET 0x480
+#define PORTSCXUSB3_OFFSET 0x540
+
+#define WAKE_ON_CONNECT_DISCONNECT_ENABLE 0x6000000
+#define RO_BITS_OFF_MASK ~0x80FE0012
+
+/*
+ * USB Port Wake Enable (UPWE) on usb attach/detach
+ * Arg0 - Port Number
+ * Arg1 - Port 1 Status and control offset
+ * Arg2 - xHCI Memory-mapped address
+ */
+Method (UPWE, 3, Serialized)
+{
+ Local0 = Arg1 + ((Arg0 - 1) * 0x10)
+
+ /* Map ((XMEM << 16) + Local0 in PSCR */
+ OperationRegion (PSCR, SystemMemory,
+ Add (ShiftLeft (Arg2, 16), Local0), 0x10)
+ Field (PSCR, DWordAcc, NoLock, Preserve)
+ {
+ PSCT, 32,
+ }
+ Local0 = PSCT
+ /*
+ * And port status/control reg with RO and RWS bits
+ * RO bits: 0, 2:3, 10:13, 24, 28:30
+ * RWS bits: 5:9, 14:16, 25:27
+ */
+ Local0 = Local0 & RO_BITS_OFF_MASK
+ /* Set WCE and WDE bits */
+ Local0 = Local0 | WAKE_ON_CONNECT_DISCONNECT_ENABLE
+ PSCT = Local0
+}
+
+/*
+ * USB Wake Enable Setup (UWES)
+ * Arg0 - Port enable bitmap
+ * Arg1 - Port 1 Status and control offset
+ * Arg2 - xHCI Memory-mapped address
+ */
+Method (UWES, 3, Serialized)
+{
+ Local0 = Arg0
+
+ While (One) {
+ FindSetRightBit (Local0, Local1)
+ If (Local1 == Zero) {
+ Break
+ }
+ UPWE (Local1, Arg1, Arg2)
+ /*
+ * Clear the lowest set bit in Local0 since it was
+ * processed.
+ */
+ Local0 = Local0 & (Local0 - 1)
+ }
+}
+
/* XHCI Controller 0:14.0 */
Device (XHCI)
@@ -10,10 +69,24 @@
Name (_PRW, Package () { GPE0_PME_B0, 3 })
+ Method (_DSW, 3)
+ {
+ UWES ((\U2WE & 0xFFF), PORTSCN_OFFSET, XMEM)
+ UWES ((\U3WE & 0x3F ), PORTSCXUSB3_OFFSET, XMEM)
+ }
+
Name (_S3D, 3) /* D3 supported in S3 */
Name (_S0W, 3) /* D3 can wake device in S0 */
Name (_S3W, 3) /* D3 can wake system from S3 */
+ OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
+ Field (XPRT, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x10),
+ , 16,
+ XMEM, 16, /* MEM_BASE */
+ }
+
Method (_PS0, 0, Serialized)
{