Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ |
| 22 | #define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ 1 |
| 23 | |
| 24 | /* Chipset types */ |
| 25 | #define HASWELL_MOBILE 0 |
| 26 | #define HASWELL_DESKTOP 1 |
| 27 | #define HASWELL_SERVER 2 |
| 28 | |
| 29 | /* Device ID for SandyBridge and IvyBridge */ |
| 30 | #define BASE_REV_SNB 0x00 |
| 31 | #define BASE_REV_IVB 0x50 |
| 32 | #define BASE_REV_MASK 0x50 |
| 33 | |
| 34 | /* SandyBridge CPU stepping */ |
| 35 | #define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ |
| 36 | #define SNB_STEP_D1 (BASE_REV_SNB + 6) |
| 37 | #define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ |
| 38 | |
| 39 | /* IvyBridge CPU stepping */ |
| 40 | #define IVB_STEP_A0 (BASE_REV_IVB + 0) |
| 41 | #define IVB_STEP_B0 (BASE_REV_IVB + 2) |
| 42 | #define IVB_STEP_C0 (BASE_REV_IVB + 4) |
| 43 | #define IVB_STEP_K0 (BASE_REV_IVB + 5) |
| 44 | #define IVB_STEP_D0 (BASE_REV_IVB + 6) |
| 45 | |
| 46 | /* Intel Enhanced Debug region must be 4MB */ |
| 47 | #define IED_SIZE 0x400000 |
| 48 | |
| 49 | /* Northbridge BARs */ |
| 50 | #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ |
| 51 | #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ |
| 52 | #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ |
| 53 | #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ |
| 54 | |
| 55 | #include <southbridge/intel/lynxpoint/pch.h> |
| 56 | |
| 57 | /* Everything below this line is ignored in the DSDT */ |
| 58 | #ifndef __ACPI__ |
| 59 | |
| 60 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
| 61 | |
| 62 | #define EPBAR 0x40 |
| 63 | #define MCHBAR 0x48 |
| 64 | #define PCIEXBAR 0x60 |
| 65 | #define DMIBAR 0x68 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 66 | |
| 67 | #define GGC 0x50 /* GMCH Graphics Control */ |
| 68 | |
| 69 | #define DEVEN 0x54 /* Device Enable */ |
| 70 | #define DEVEN_PEG60 (1 << 13) |
| 71 | #define DEVEN_IGD (1 << 4) |
| 72 | #define DEVEN_PEG10 (1 << 3) |
| 73 | #define DEVEN_PEG11 (1 << 2) |
| 74 | #define DEVEN_PEG12 (1 << 1) |
| 75 | #define DEVEN_HOST (1 << 0) |
| 76 | |
| 77 | #define PAM0 0x80 |
| 78 | #define PAM1 0x81 |
| 79 | #define PAM2 0x82 |
| 80 | #define PAM3 0x83 |
| 81 | #define PAM4 0x84 |
| 82 | #define PAM5 0x85 |
| 83 | #define PAM6 0x86 |
| 84 | |
| 85 | #define LAC 0x87 /* Legacy Access Control */ |
| 86 | #define SMRAM 0x88 /* System Management RAM Control */ |
| 87 | #define D_OPEN (1 << 6) |
| 88 | #define D_CLS (1 << 5) |
| 89 | #define D_LCK (1 << 4) |
| 90 | #define G_SMRAME (1 << 3) |
| 91 | #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) |
| 92 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 93 | #define MESEG_BASE 0x70 /* Management Engine Base. */ |
| 94 | #define MESEG_LIMIT 0x78 /* Management Engine Limit. */ |
| 95 | #define REMAPBASE 0x90 /* Remap base. */ |
| 96 | #define REMAPLIMIT 0x98 /* Remap limit. */ |
| 97 | #define TOM 0xa0 /* Top of DRAM in memory controller space. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 98 | #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 99 | #define BDSM 0xb0 /* Base Data Stolen Memory */ |
| 100 | #define BGSM 0xb4 /* Base GTT Stolen Memory */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 101 | #define TSEG 0xb8 /* TSEG base */ |
| 102 | #define TOLUD 0xbc /* Top of Low Used Memory */ |
| 103 | |
| 104 | #define SKPAD 0xdc /* Scratchpad Data */ |
| 105 | |
| 106 | /* Device 0:1.0 PCI configuration space (PCI Express) */ |
| 107 | |
| 108 | #define BCTRL1 0x3e /* 16bit */ |
| 109 | |
| 110 | |
| 111 | /* Device 0:2.0 PCI configuration space (Graphics Device) */ |
| 112 | |
| 113 | #define MSAC 0x62 /* Multi Size Aperture Control */ |
| 114 | #define SWSCI 0xe8 /* SWSCI enable */ |
| 115 | #define ASLS 0xfc /* OpRegion Base */ |
| 116 | |
| 117 | /* |
| 118 | * MCHBAR |
| 119 | */ |
| 120 | |
| 121 | #define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) |
| 122 | #define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) |
| 123 | #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) |
| 124 | #define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or)) |
| 125 | |
| 126 | #define SSKPD 0x5d14 /* 16bit (scratchpad) */ |
| 127 | #define BIOS_RESET_CPL 0x5da8 /* 8bit */ |
| 128 | |
| 129 | /* |
| 130 | * EPBAR - Egress Port Root Complex Register Block |
| 131 | */ |
| 132 | |
| 133 | #define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) |
| 134 | #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) |
| 135 | #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) |
| 136 | |
| 137 | #define EPPVCCAP1 0x004 /* 32bit */ |
| 138 | #define EPPVCCAP2 0x008 /* 32bit */ |
| 139 | |
| 140 | #define EPVC0RCAP 0x010 /* 32bit */ |
| 141 | #define EPVC0RCTL 0x014 /* 32bit */ |
| 142 | #define EPVC0RSTS 0x01a /* 16bit */ |
| 143 | |
| 144 | #define EPVC1RCAP 0x01c /* 32bit */ |
| 145 | #define EPVC1RCTL 0x020 /* 32bit */ |
| 146 | #define EPVC1RSTS 0x026 /* 16bit */ |
| 147 | |
| 148 | #define EPVC1MTS 0x028 /* 32bit */ |
| 149 | #define EPVC1IST 0x038 /* 64bit */ |
| 150 | |
| 151 | #define EPESD 0x044 /* 32bit */ |
| 152 | |
| 153 | #define EPLE1D 0x050 /* 32bit */ |
| 154 | #define EPLE1A 0x058 /* 64bit */ |
| 155 | #define EPLE2D 0x060 /* 32bit */ |
| 156 | #define EPLE2A 0x068 /* 64bit */ |
| 157 | |
| 158 | #define PORTARB 0x100 /* 256bit */ |
| 159 | |
| 160 | /* |
| 161 | * DMIBAR |
| 162 | */ |
| 163 | |
| 164 | #define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) |
| 165 | #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) |
| 166 | #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) |
| 167 | |
| 168 | #define DMIVCECH 0x000 /* 32bit */ |
| 169 | #define DMIPVCCAP1 0x004 /* 32bit */ |
| 170 | #define DMIPVCCAP2 0x008 /* 32bit */ |
| 171 | |
| 172 | #define DMIPVCCCTL 0x00c /* 16bit */ |
| 173 | |
| 174 | #define DMIVC0RCAP 0x010 /* 32bit */ |
| 175 | #define DMIVC0RCTL0 0x014 /* 32bit */ |
| 176 | #define DMIVC0RSTS 0x01a /* 16bit */ |
| 177 | |
| 178 | #define DMIVC1RCAP 0x01c /* 32bit */ |
| 179 | #define DMIVC1RCTL 0x020 /* 32bit */ |
| 180 | #define DMIVC1RSTS 0x026 /* 16bit */ |
| 181 | |
| 182 | #define DMILE1D 0x050 /* 32bit */ |
| 183 | #define DMILE1A 0x058 /* 64bit */ |
| 184 | #define DMILE2D 0x060 /* 32bit */ |
| 185 | #define DMILE2A 0x068 /* 64bit */ |
| 186 | |
| 187 | #define DMILCAP 0x084 /* 32bit */ |
| 188 | #define DMILCTL 0x088 /* 16bit */ |
| 189 | #define DMILSTS 0x08a /* 16bit */ |
| 190 | |
| 191 | #define DMICTL1 0x0f0 /* 32bit */ |
| 192 | #define DMICTL2 0x0fc /* 32bit */ |
| 193 | |
| 194 | #define DMICC 0x208 /* 32bit */ |
| 195 | |
| 196 | #define DMIDRCCFG 0xeb4 /* 32bit */ |
| 197 | |
| 198 | #ifndef __ASSEMBLER__ |
| 199 | static inline void barrier(void) { asm("" ::: "memory"); } |
| 200 | |
| 201 | struct ied_header { |
| 202 | char signature[10]; |
| 203 | u32 size; |
| 204 | u8 reserved[34]; |
| 205 | } __attribute__ ((packed)); |
| 206 | |
Aaron Durbin | 21efd8c | 2013-01-17 09:39:39 -0600 | [diff] [blame^] | 207 | #define PCI_DEVICE_ID_HSW_MOBILE 0x0c04 |
| 208 | #define PCI_DEVICE_ID_HSW_ULT 0x0a04 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 209 | |
| 210 | #ifdef __SMM__ |
| 211 | void intel_northbridge_haswell_finalize_smm(void); |
| 212 | #else /* !__SMM__ */ |
| 213 | int bridge_silicon_revision(void); |
| 214 | void haswell_early_initialization(int chipset_type); |
| 215 | void haswell_late_initialization(void); |
| 216 | |
| 217 | /* debugging functions */ |
| 218 | void print_pci_devices(void); |
| 219 | void dump_pci_device(unsigned dev); |
| 220 | void dump_pci_devices(void); |
| 221 | void dump_spd_registers(void); |
| 222 | void dump_mem(unsigned start, unsigned end); |
| 223 | void report_platform_info(void); |
| 224 | #endif /* !__SMM__ */ |
| 225 | |
| 226 | |
| 227 | #define MRC_DATA_ALIGN 0x1000 |
| 228 | #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) |
| 229 | |
| 230 | struct mrc_data_container { |
| 231 | u32 mrc_signature; // "MRCD" |
| 232 | u32 mrc_data_size; // Actual total size of this structure |
| 233 | u32 mrc_checksum; // IP style checksum |
| 234 | u32 reserved; // For header alignment |
| 235 | u8 mrc_data[0]; // Variable size, platform/run time dependent. |
| 236 | } __attribute__ ((packed)); |
| 237 | |
| 238 | struct mrc_data_container *find_current_mrc_cache(void); |
| 239 | #if !defined(__PRE_RAM__) |
| 240 | void update_mrc_cache(void); |
| 241 | |
| 242 | #include "gma.h" |
| 243 | int init_igd_opregion(igd_opregion_t *igd_opregion); |
| 244 | #endif |
| 245 | |
| 246 | #endif |
| 247 | #endif |
| 248 | #endif |