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Lee Leahy5cb9dda2015-05-01 10:34:54 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
5 * Copyright (C) 2015 Intel Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy5cb9dda2015-05-01 10:34:54 -070015 */
16
17#ifndef ONBOARD_H
18#define ONBOARD_H
19
20#include "irqroute.h"
21
22/*
23 * Calculation of gpio based irq.
24 * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE
25 * Max direct irq (MAX_DIRECT_IRQ) is 114.
26 * Size of gpio banks are
27 * GPSW_SIZE = 98
28 * GPNC_SIZE = 73
29 * GPEC_SIZE = 27
30 * GPSE_SIZE = 86
31 */
32
33/*
34 * gpio based irq for kbd, 17th index in North Bank
35 * MAX_DIRECT_IRQ + GPSW_SIZE + 18
36 */
37/* ToDo: change kbd irq to gpio bank index */
38#define BOARD_I8042_IRQ 182
39
Hannah Williams103f00d2016-01-25 14:36:56 -080040#define BOARD_TOUCH_IRQ 184
Lee Leahy5cb9dda2015-05-01 10:34:54 -070041
42
43/* Audio: Gpio index in SW bank */
44#define JACK_DETECT_GPIO_INDEX 95
45/* SCI: Gpio index in N bank */
46#define BOARD_SCI_GPIO_INDEX 15
47/* Trackpad: Gpio index in N bank */
48#define BOARD_TRACKPAD_GPIO_INDEX 18
49
50#define BOARD_TRACKPAD_NAME "trackpad"
51#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1)
52#define BOARD_TRACKPAD_I2C_BUS 5
53#define BOARD_TRACKPAD_I2C_ADDR 0x15
54
55#define BOARD_TOUCHSCREEN_NAME "touchscreen"
56#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2)
57#define BOARD_TOUCHSCREEN_I2C_BUS 0
58#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */
59
Lee Leahy5cb9dda2015-05-01 10:34:54 -070060
61
62/* SD CARD gpio */
63#define SDCARD_CD 81
64
65#define AUDIO_CODEC_HID "10EC5650"
66#define AUDIO_CODEC_CID "10EC5650"
67#define AUDIO_CODEC_DDN "RTEK Codec Controller "
68#define AUDIO_CODEC_I2C_ADDR 0x1A
69
Lee Leahy5cb9dda2015-05-01 10:34:54 -070070#define BCRD2_PMIC_I2C_BUS 0x01
71
Divagar Mohandass060bc792015-09-29 15:01:58 +053072#define DPTF_CPU_PASSIVE 88
73#define DPTF_CPU_CRITICAL 90
74
Lee Leahy5cb9dda2015-05-01 10:34:54 -070075#endif