mainboard/intel: Add Braswell based Strago board
Add the initial files to support the Intel RVP for Braswell.
Matches chromium tree at 927026db
This board uses the Braswell FSP 1.1 image and does not build without
the FspUpdVpd.h file.
BRANCH=none
BUG=None
TEST=Build and run ChromeOS on strago
Change-Id: I5cb2efe3d8adf919165c62b25e08c544b316a05a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10052
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h
new file mode 100755
index 0000000..ec75578
--- /dev/null
+++ b/src/mainboard/intel/strago/onboard.h
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include "irqroute.h"
+
+/*
+ * Calculation of gpio based irq.
+ * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE
+ * Max direct irq (MAX_DIRECT_IRQ) is 114.
+ * Size of gpio banks are
+ * GPSW_SIZE = 98
+ * GPNC_SIZE = 73
+ * GPEC_SIZE = 27
+ * GPSE_SIZE = 86
+ */
+
+/*
+ * gpio based irq for kbd, 17th index in North Bank
+ * MAX_DIRECT_IRQ + GPSW_SIZE + 18
+ */
+/* ToDo: change kbd irq to gpio bank index */
+#define BOARD_I8042_IRQ 182
+
+#define BOARD_TOUCH_IRQ 156
+#define BOARD_DVT_TOUCH_IRQ 184
+
+
+/* Audio: Gpio index in SW bank */
+#define JACK_DETECT_GPIO_INDEX 95
+/* SCI: Gpio index in N bank */
+#define BOARD_SCI_GPIO_INDEX 15
+/* Trackpad: Gpio index in N bank */
+#define BOARD_TRACKPAD_GPIO_INDEX 18
+
+#define BOARD_TRACKPAD_NAME "trackpad"
+#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS 5
+#define BOARD_TRACKPAD_I2C_ADDR 0x15
+
+#define BOARD_TOUCHSCREEN_NAME "touchscreen"
+#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2)
+#define BOARD_TOUCHSCREEN_I2C_BUS 0
+#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */
+
+#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET)
+
+
+/* SD CARD gpio */
+#define SDCARD_CD 81
+
+#define AUDIO_CODEC_HID "10EC5650"
+#define AUDIO_CODEC_CID "10EC5650"
+#define AUDIO_CODEC_DDN "RTEK Codec Controller "
+#define AUDIO_CODEC_I2C_ADDR 0x1A
+
+#define BOARD_EVT 0x02
+#define BOARD_DVT 0x03
+#define BOARD_BCRD2 0x04
+
+#define BCRD2_PMIC_I2C_BUS 0x01
+
+#endif