Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * Copyright (C) 2015 Intel Corporation. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
Duncan Laurie | 74b964e | 2015-09-04 10:41:02 -0700 | [diff] [blame] | 17 | #ifndef MAINBOARD_SPD_H |
Rizwan Qureshi | 5ff7390 | 2016-08-24 20:50:54 +0530 | [diff] [blame] | 18 | |
| 19 | #include <gpio.h> |
| 20 | #include "../gpio.h" |
| 21 | |
Duncan Laurie | 74b964e | 2015-09-04 10:41:02 -0700 | [diff] [blame] | 22 | #define MAINBOARD_SPD_H |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 23 | |
| 24 | #define SPD_LEN 256 |
| 25 | |
| 26 | #define SPD_DRAM_TYPE 2 |
| 27 | #define SPD_DRAM_DDR3 0x0b |
| 28 | #define SPD_DRAM_LPDDR3 0xf1 |
| 29 | #define SPD_DENSITY_BANKS 4 |
| 30 | #define SPD_ADDRESSING 5 |
| 31 | #define SPD_ORGANIZATION 7 |
| 32 | #define SPD_BUS_DEV_WIDTH 8 |
| 33 | #define SPD_PART_OFF 128 |
| 34 | #define SPD_PART_LEN 18 |
Duncan Laurie | 74b964e | 2015-09-04 10:41:02 -0700 | [diff] [blame] | 35 | #define SPD_MANU_OFF 148 |
Lee Leahy | c421041 | 2015-06-29 11:37:56 -0700 | [diff] [blame] | 36 | |
Brandon Breitenstein | ad77bf9 | 2015-10-27 13:49:14 -0700 | [diff] [blame] | 37 | #define HYNIX_SINGLE_CHAN 0x1 |
| 38 | #define SAMSUNG_SINGLE_CHAN 0x4 |
| 39 | #define MIC_SINGLE_CHAN 0x5 |
Rizwan Qureshi | 5ff7390 | 2016-08-24 20:50:54 +0530 | [diff] [blame] | 40 | |
| 41 | /* PCH_MEM_CFG[3:0] */ |
| 42 | #define MAX_MEMORY_CONFIG 0x10 |
| 43 | #define RCOMP_TARGET_PARAMS 0x5 |
| 44 | #define K4E6E304EE_MEM_ID 0x3 |
| 45 | |
| 46 | static inline int get_spd_index(void) { |
| 47 | /* PCH_MEM_CFG[3:0] */ |
| 48 | gpio_t spd_gpios[] = { |
| 49 | GPIO_MEM_CONFIG_0, |
| 50 | GPIO_MEM_CONFIG_1, |
| 51 | GPIO_MEM_CONFIG_2, |
| 52 | GPIO_MEM_CONFIG_3, |
| 53 | }; |
| 54 | return (gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))); |
| 55 | } |
| 56 | void mainboard_fill_dq_map_data(void *dq_map_ptr); |
| 57 | void mainboard_fill_dqs_map_data(void *dqs_map_ptr); |
| 58 | void mainboard_fill_rcomp_res_data(void *rcomp_ptr); |
| 59 | void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); |
| 60 | uintptr_t mainboard_get_spd_data(void); |
| 61 | int mainboard_has_dual_channel_mem(void); |
Duncan Laurie | 74b964e | 2015-09-04 10:41:02 -0700 | [diff] [blame] | 62 | #endif |