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review.coreboot.org / coreboot / a50ced2eba20a007fa5b486c251c252ad09868cf / . / src / mainboard / amd / inagua / dsdt.asl
blob: 0cf657f23a23a319c4b8187e916b81a6f93d0161 [file] [log] [blame]
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]14 */
15
16/* DefinitionBlock Statement */
17DefinitionBlock (
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]18 "DSDT.AML", /* Output filename */
19 "DSDT", /* Signature */
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]20 0x02, /* DSDT Revision, needs to be 2 for 64bit */
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]21 "AMD ", /* OEMID */
22 "COREBOOT", /* TABLE ID */
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]23 0x00010001 /* OEM Revision */
24 )
25{ /* Start of ASL file */
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]26 /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300[diff] [blame]27
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]28 #include "acpi/mainboard.asl"
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]29
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]30 #include <cpu/amd/agesa/family14/acpi/cpu.asl>
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]31
32 #include "acpi/routing.asl"
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300[diff] [blame]33
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]34 Scope(\_SB) {
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]35 /* global utility methods expected within the \_SB scope */
36 #include <arch/x86/acpi/globutil.asl>
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]37
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]38 Device(PCI0) {
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]39
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]40 /* Describe the AMD Northbridge */
41 #include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]42
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]43 /* Describe the AMD Fusion Controller Hub Southbridge */
44 #include <southbridge/amd/cimx/sb800/acpi/fch.asl>
45
Edward O'Callaghan99e2bf82014-04-06 02:53:49 +1100[diff] [blame]46 /* Primary (and only) IDE channel */
47 Device(IDEC) {
48 Name(_ADR, 0x00140001)
49 #include "acpi/ide.asl"
50 } /* end IDEC */
51
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]52 }
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]53 } /* End Scope(_SB) */
54
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]55 /* Contains the supported sleep states for this chipset */
56 #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]57
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]58 /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
59 #include "acpi/sleep.asl"
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]60
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]61 #include "acpi/gpe.asl"
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]62}
63/* End of ASL file */