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review.coreboot.org / coreboot / ecd842491972a523a704faef3badd74d9a70a490 / . / src / mainboard / amd / inagua / dsdt.asl
blob: f7c7bb2de3512f8ddbd3bda1c1c3aa64b9a91eda [file] [log] [blame]
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +0100[diff] [blame]17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]18 */
19
20/* DefinitionBlock Statement */
21DefinitionBlock (
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]22 "DSDT.AML", /* Output filename */
23 "DSDT", /* Signature */
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]24 0x02, /* DSDT Revision, needs to be 2 for 64bit */
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]25 "AMD ", /* OEMID */
26 "COREBOOT", /* TABLE ID */
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]27 0x00010001 /* OEM Revision */
28 )
29{ /* Start of ASL file */
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]30 /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300[diff] [blame^]31
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]32 #include "acpi/mainboard.asl"
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]33
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]34 #include <cpu/amd/agesa/family14/acpi/cpu.asl>
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]35
36 #include "acpi/routing.asl"
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300[diff] [blame^]37
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]38 Scope(\_SB) {
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]39 /* global utility methods expected within the \_SB scope */
40 #include <arch/x86/acpi/globutil.asl>
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]41
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]42 Device(PCI0) {
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]43
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]44 /* Describe the AMD Northbridge */
45 #include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]46
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]47 /* Describe the AMD Fusion Controller Hub Southbridge */
48 #include <southbridge/amd/cimx/sb800/acpi/fch.asl>
49
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]50 }
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]51 } /* End Scope(_SB) */
52
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]53 /* Contains the supported sleep states for this chipset */
54 #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]55
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]56 /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
57 #include "acpi/sleep.asl"
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]58
Mike Loptienba7ed4b2013-03-29 13:33:39 -0600[diff] [blame]59 #include "acpi/gpe.asl"
60 #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
61 #include "acpi/thermal.asl"
Frank Vibrans69da1b62011-02-14 19:04:45 +0000[diff] [blame]62}
63/* End of ASL file */