blob: 25520b236834c72d9b31ffb821cd8e90c936082c [file] [log] [blame]
Frank Vibrans69da1b62011-02-14 19:04:45 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +010017 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Frank Vibrans69da1b62011-02-14 19:04:45 +000018 */
19
20/* DefinitionBlock Statement */
21DefinitionBlock (
Mike Loptienba7ed4b2013-03-29 13:33:39 -060022 "DSDT.AML", /* Output filename */
23 "DSDT", /* Signature */
Frank Vibrans69da1b62011-02-14 19:04:45 +000024 0x02, /* DSDT Revision, needs to be 2 for 64bit */
Mike Loptienba7ed4b2013-03-29 13:33:39 -060025 "AMD ", /* OEMID */
26 "COREBOOT", /* TABLE ID */
Frank Vibrans69da1b62011-02-14 19:04:45 +000027 0x00010001 /* OEM Revision */
28 )
29{ /* Start of ASL file */
Mike Loptienba7ed4b2013-03-29 13:33:39 -060030 /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
Kyösti Mälkkiecd84242013-09-13 07:57:49 +030031
Mike Loptienba7ed4b2013-03-29 13:33:39 -060032 #include "acpi/mainboard.asl"
Frank Vibrans69da1b62011-02-14 19:04:45 +000033
Mike Loptienba7ed4b2013-03-29 13:33:39 -060034 #include <cpu/amd/agesa/family14/acpi/cpu.asl>
Frank Vibrans69da1b62011-02-14 19:04:45 +000035
36 #include "acpi/routing.asl"
Kyösti Mälkkiecd84242013-09-13 07:57:49 +030037
Frank Vibrans69da1b62011-02-14 19:04:45 +000038 Scope(\_SB) {
Mike Loptienba7ed4b2013-03-29 13:33:39 -060039 /* global utility methods expected within the \_SB scope */
40 #include <arch/x86/acpi/globutil.asl>
Frank Vibrans69da1b62011-02-14 19:04:45 +000041
Mike Loptienba7ed4b2013-03-29 13:33:39 -060042 Device(PCI0) {
Frank Vibrans69da1b62011-02-14 19:04:45 +000043
Mike Loptienba7ed4b2013-03-29 13:33:39 -060044 /* Describe the AMD Northbridge */
45 #include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
Frank Vibrans69da1b62011-02-14 19:04:45 +000046
Mike Loptienba7ed4b2013-03-29 13:33:39 -060047 /* Describe the AMD Fusion Controller Hub Southbridge */
48 #include <southbridge/amd/cimx/sb800/acpi/fch.asl>
49
Edward O'Callaghan99e2bf82014-04-06 02:53:49 +110050 /* Primary (and only) IDE channel */
51 Device(IDEC) {
52 Name(_ADR, 0x00140001)
53 #include "acpi/ide.asl"
54 } /* end IDEC */
55
Frank Vibrans69da1b62011-02-14 19:04:45 +000056 }
Frank Vibrans69da1b62011-02-14 19:04:45 +000057 } /* End Scope(_SB) */
58
Mike Loptienba7ed4b2013-03-29 13:33:39 -060059 /* Contains the supported sleep states for this chipset */
60 #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
Frank Vibrans69da1b62011-02-14 19:04:45 +000061
Mike Loptienba7ed4b2013-03-29 13:33:39 -060062 /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
63 #include "acpi/sleep.asl"
Frank Vibrans69da1b62011-02-14 19:04:45 +000064
Mike Loptienba7ed4b2013-03-29 13:33:39 -060065 #include "acpi/gpe.asl"
66 #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
67 #include "acpi/thermal.asl"
Frank Vibrans69da1b62011-02-14 19:04:45 +000068}
69/* End of ASL file */