Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 2 | |
| 3 | /** |
| 4 | * @file post_codes.h |
Martin Roth | 2507820 | 2015-01-06 21:05:23 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 8 | * This aims to be a central point for POST codes used throughout coreboot. |
| 9 | * All POST codes should be declared here as macros, and post_code() should |
| 10 | * be used with the macros instead of hardcoded values. This allows us to |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 11 | * quickly reference POST codes when nothing is working |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 12 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 13 | * The format for a POST code macro is |
| 14 | * #define POST_WHAT_WE_COMMUNICATE_IS_HAPPENING_WHEN_THIS_CODE_IS_POSTED |
| 15 | * Lets's keep it at POST_* instead of POST_CODE_* |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 16 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 17 | * This file is also included by early assembly files. Only use #define s; |
| 18 | * no function prototypes allowed here |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 19 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 20 | * DOCUMENTATION: |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 21 | * Please document any and all post codes using Doxygen style comments. We |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 22 | * want to be able to generate a verbose enough documentation that is useful |
| 23 | * during debugging. Failure to do so will result in your patch being rejected |
| 24 | * without any explanation or effort on part of the maintainers. |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 25 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 26 | */ |
Martin Roth | 2507820 | 2015-01-06 21:05:23 -0700 | [diff] [blame] | 27 | |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 28 | #ifndef POST_CODES_H |
| 29 | #define POST_CODES_H |
| 30 | |
| 31 | /** |
| 32 | * \brief Entry into 'crt0.s'. reset code jumps to here |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 33 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 34 | * First instruction that gets executed after the reset vector jumps. |
| 35 | * This indicates that the reset vector points to the correct code segment. |
| 36 | */ |
| 37 | #define POST_RESET_VECTOR_CORRECT 0x01 |
| 38 | |
| 39 | /** |
| 40 | * \brief Entry into protected mode |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 41 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 42 | * Preparing to enter protected mode. This is POSTed right before changing to |
| 43 | * protected mode. |
| 44 | */ |
| 45 | #define POST_ENTER_PROTECTED_MODE 0x10 |
| 46 | |
| 47 | /** |
| 48 | * \brief Start copying coreboot to RAM with decompression if compressed |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 49 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 50 | * POSTed before ramstage is about to be loaded into memory |
| 51 | */ |
Lee Leahy | 84d20d0 | 2017-03-07 15:00:18 -0800 | [diff] [blame] | 52 | #define POST_PREPARE_RAMSTAGE 0x11 |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 53 | |
| 54 | /** |
| 55 | * \brief Copy/decompression finished; jumping to RAM |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 56 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 57 | * This is called after ramstage is loaded in memory, and before |
| 58 | * the code jumps there. This represents the end of romstage. |
| 59 | */ |
| 60 | #define POST_RAMSTAGE_IS_PREPARED 0x12 |
| 61 | |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 62 | /** |
| 63 | * \brief Entry into c_start |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 64 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 65 | * c_start.S is the first code executing in ramstage. |
| 66 | */ |
| 67 | #define POST_ENTRY_C_START 0x13 |
| 68 | |
| 69 | /** |
Furquan Shaikh | 9706359 | 2018-10-16 11:49:16 -0700 | [diff] [blame] | 70 | * \brief Pre-memory init preparation start |
| 71 | * |
| 72 | * Post code emitted in romstage before making callbacks to allow SoC/mainboard |
| 73 | * to prepare params for FSP memory init. |
| 74 | */ |
| 75 | #define POST_MEM_PREINIT_PREP_START 0x34 |
| 76 | |
| 77 | /** |
| 78 | * \brief Pre-memory init preparation end |
| 79 | * |
| 80 | * Post code emitted in romstage after returning from SoC/mainboard callbacks |
| 81 | * to prepare params for FSP memory init. |
| 82 | */ |
| 83 | #define POST_MEM_PREINIT_PREP_END 0x36 |
| 84 | |
| 85 | /** |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 86 | * \brief Console is initialized |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 87 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 88 | * The console is initialized and is ready for usage |
| 89 | */ |
| 90 | #define POST_CONSOLE_READY 0x39 |
| 91 | |
| 92 | /** |
| 93 | * \brief Console boot message succeeded |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 94 | * |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 95 | * First console message has been successfully sent through the console backend |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 96 | * driver. |
| 97 | */ |
| 98 | #define POST_CONSOLE_BOOT_MSG 0x40 |
| 99 | |
| 100 | /** |
Vikram Narayanan | 0713ca3 | 2012-01-23 01:44:44 +0530 | [diff] [blame] | 101 | * \brief Before enabling the cache |
| 102 | * |
| 103 | * Going to enable the cache |
| 104 | */ |
| 105 | #define POST_ENABLING_CACHE 0x60 |
| 106 | |
| 107 | /** |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 108 | * \brief Before Device Probe |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 109 | * |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 110 | * Boot State Machine: bs_pre_device() |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 111 | */ |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 112 | #define POST_BS_PRE_DEVICE 0x70 |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 113 | |
| 114 | /** |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 115 | * \brief Initializing Chips |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 116 | * |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 117 | * Boot State Machine: bs_dev_init_chips() |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 118 | */ |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 119 | #define POST_BS_DEV_INIT_CHIPS 0x71 |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 120 | |
| 121 | /** |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 122 | * \brief Starting Device Enumeration |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 123 | * |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 124 | * Boot State Machine: bs_dev_enumerate() |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 125 | */ |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 126 | #define POST_BS_DEV_ENUMERATE 0x72 |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 127 | |
| 128 | /** |
Elyes HAOUAS | 5f73e22 | 2020-01-15 21:13:45 +0100 | [diff] [blame] | 129 | * \brief Device Resource Allocation |
Stefan Reinauer | 52095f5 | 2012-08-07 13:14:20 -0700 | [diff] [blame] | 130 | * |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 131 | * Boot State Machine: bs_dev_resources() |
Stefan Reinauer | 52095f5 | 2012-08-07 13:14:20 -0700 | [diff] [blame] | 132 | */ |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 133 | #define POST_BS_DEV_RESOURCES 0x73 |
| 134 | |
| 135 | /** |
| 136 | * \brief Device Enable |
| 137 | * |
| 138 | * Boot State Machine: bs_dev_enable() |
| 139 | */ |
| 140 | #define POST_BS_DEV_ENABLE 0x74 |
| 141 | |
| 142 | /** |
| 143 | * \brief Device Initialization |
| 144 | * |
| 145 | * Boot State Machine: bs_dev_init() |
| 146 | */ |
| 147 | #define POST_BS_DEV_INIT 0x75 |
| 148 | |
| 149 | /** |
| 150 | * \brief After Device Probe |
| 151 | * |
| 152 | * Boot State Machine: bs_post_device() |
| 153 | */ |
| 154 | #define POST_BS_POST_DEVICE 0x76 |
| 155 | |
| 156 | /** |
| 157 | * \brief OS Resume Check |
| 158 | * |
| 159 | * Boot State Machine: bs_os_resume_check() |
| 160 | */ |
| 161 | #define POST_BS_OS_RESUME_CHECK 0x77 |
| 162 | |
| 163 | /** |
| 164 | * \brief OS Resume |
| 165 | * |
| 166 | * Boot State Machine: bs_os_resume() |
| 167 | */ |
| 168 | #define POST_BS_OS_RESUME 0x78 |
| 169 | |
| 170 | /** |
| 171 | * \brief Write Tables |
| 172 | * |
| 173 | * Boot State Machine: bs_write_tables() |
| 174 | */ |
| 175 | #define POST_BS_WRITE_TABLES 0x79 |
| 176 | |
| 177 | /** |
Sindhoor Tilak | e5f25ce | 2020-06-19 20:46:40 -0400 | [diff] [blame] | 178 | * \brief Pre call to RAM stage main() |
| 179 | * |
| 180 | * POSTed right before RAM stage main() is called from c_start.S |
| 181 | */ |
| 182 | #define POST_PRE_HARDWAREMAIN 0x79 |
| 183 | |
| 184 | /** |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 185 | * \brief Load Payload |
| 186 | * |
| 187 | * Boot State Machine: bs_payload_load() |
| 188 | */ |
| 189 | #define POST_BS_PAYLOAD_LOAD 0x7a |
| 190 | |
| 191 | /** |
| 192 | * \brief Boot Payload |
| 193 | * |
| 194 | * Boot State Machine: bs_payload_boot() |
| 195 | */ |
| 196 | #define POST_BS_PAYLOAD_BOOT 0x7b |
Stefan Reinauer | 52095f5 | 2012-08-07 13:14:20 -0700 | [diff] [blame] | 197 | |
| 198 | /** |
Subrata Banik | a2cf341 | 2021-05-04 23:36:36 +0530 | [diff] [blame^] | 199 | * \brief Entry into coreboot in RAM stage main() |
| 200 | * |
| 201 | * This is the first call in hardwaremain.c. If this code is POSTed, then |
| 202 | * ramstage has successfully loaded and started executing. |
| 203 | */ |
| 204 | #define POST_ENTRY_RAMSTAGE 0x80 |
| 205 | |
| 206 | /** |
Aaron Durbin | 96b3c6f | 2016-11-10 21:09:25 -0600 | [diff] [blame] | 207 | * \brief Before calling FSP Notify before End of Firmware |
| 208 | * |
| 209 | * Going to call into FSP binary for Notify phase |
| 210 | */ |
| 211 | #define POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE 0x88 |
| 212 | |
| 213 | /** |
| 214 | * \brief Before calling FSP Notify after End of Firmware |
| 215 | * |
| 216 | * Going to call into FSP binary for Notify phase |
| 217 | */ |
| 218 | #define POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE 0x89 |
| 219 | |
| 220 | /** |
Duncan Laurie | fb50983 | 2015-11-22 14:53:57 -0800 | [diff] [blame] | 221 | * \brief Before calling FSP TempRamInit |
| 222 | * |
| 223 | * Going to call into FSP binary for TempRamInit phase |
| 224 | */ |
| 225 | #define POST_FSP_TEMP_RAM_INIT 0x90 |
| 226 | |
| 227 | /** |
| 228 | * \brief Before calling FSP TempRamExit |
| 229 | * |
| 230 | * Going to call into FSP binary for TempRamExit phase |
| 231 | */ |
| 232 | #define POST_FSP_TEMP_RAM_EXIT 0x91 |
| 233 | |
| 234 | /** |
| 235 | * \brief Before calling FSP MemoryInit |
| 236 | * |
| 237 | * Going to call into FSP binary for MemoryInit phase |
| 238 | */ |
| 239 | #define POST_FSP_MEMORY_INIT 0x92 |
| 240 | |
| 241 | /** |
| 242 | * \brief Before calling FSP SiliconInit |
| 243 | * |
| 244 | * Going to call into FSP binary for SiliconInit phase |
| 245 | */ |
| 246 | #define POST_FSP_SILICON_INIT 0x93 |
| 247 | |
| 248 | /** |
| 249 | * \brief Before calling FSP Notify before resource allocation |
| 250 | * |
| 251 | * Going to call into FSP binary for Notify phase |
| 252 | */ |
| 253 | #define POST_FSP_NOTIFY_BEFORE_ENUMERATE 0x94 |
| 254 | |
| 255 | /** |
| 256 | * \brief Before calling FSP Notify before finalize |
| 257 | * |
| 258 | * Going to call into FSP binary for Notify phase |
| 259 | */ |
| 260 | #define POST_FSP_NOTIFY_BEFORE_FINALIZE 0x95 |
| 261 | |
| 262 | /** |
Hannah Williams | 4cff1d5 | 2016-06-08 14:29:47 -0700 | [diff] [blame] | 263 | * \brief Indicate OS _PTS entry |
| 264 | * |
| 265 | * Called from _PTS asl method |
| 266 | */ |
| 267 | #define POST_OS_ENTER_PTS 0x96 |
| 268 | |
| 269 | /** |
| 270 | * \brief Indicate OS _WAK entry |
| 271 | * |
| 272 | * Called from within _WAK method |
| 273 | */ |
| 274 | #define POST_OS_ENTER_WAKE 0x97 |
| 275 | |
| 276 | /** |
Subrata Banik | 0755ab9 | 2017-07-12 15:31:06 +0530 | [diff] [blame] | 277 | * \brief After calling FSP MemoryInit |
| 278 | * |
| 279 | * FSP binary returned from MemoryInit phase |
| 280 | */ |
| 281 | #define POST_FSP_MEMORY_EXIT 0x98 |
| 282 | |
| 283 | /** |
| 284 | * \brief After calling FSP SiliconInit |
| 285 | * |
| 286 | * FSP binary returned from SiliconInit phase |
| 287 | */ |
| 288 | #define POST_FSP_SILICON_EXIT 0x99 |
| 289 | |
| 290 | /** |
Subrata Banik | 33d9c4a | 2020-05-26 18:26:54 +0530 | [diff] [blame] | 291 | * \brief Before calling FSP Multiphase SiliconInit |
| 292 | * |
| 293 | * Going to call into FSP binary for Multiple phase SI Init |
| 294 | */ |
| 295 | #define POST_FSP_MULTI_PHASE_SI_INIT_ENTRY 0xa0 |
| 296 | |
| 297 | /** |
| 298 | * \brief After calling FSP Multiphase SiliconInit |
| 299 | * |
| 300 | * FSP binary returned from Multiple phase SI Init |
| 301 | */ |
| 302 | #define POST_FSP_MULTI_PHASE_SI_INIT_EXIT 0xa1 |
| 303 | |
| 304 | /** |
Keith Short | 7006458 | 2019-05-06 16:12:57 -0600 | [diff] [blame] | 305 | * \brief Invalid or corrupt ROM |
| 306 | * |
| 307 | * Set if firmware failed to find or validate a resource that is stored in ROM. |
| 308 | */ |
| 309 | #define POST_INVALID_ROM 0xe0 |
| 310 | |
| 311 | /** |
Keith Short | 1835bf0 | 2019-05-16 11:46:27 -0600 | [diff] [blame] | 312 | * \brief Invalid or corrupt CBFS |
| 313 | * |
| 314 | * Set if firmware failed to find or validate a resource that is stored in CBFS. |
| 315 | */ |
| 316 | #define POST_INVALID_CBFS 0xe1 |
| 317 | |
| 318 | /** |
Keith Short | bb41aba | 2019-05-16 14:07:43 -0600 | [diff] [blame] | 319 | * \brief Vendor binary error |
| 320 | * |
| 321 | * Set if firmware failed to find or validate a vendor binary, or the binary |
| 322 | * generated a fatal error. |
| 323 | */ |
| 324 | #define POST_INVALID_VENDOR_BINARY 0xe2 |
| 325 | |
| 326 | /** |
Keith Short | 2430263 | 2019-05-16 14:08:31 -0600 | [diff] [blame] | 327 | * \brief RAM failure |
| 328 | * |
| 329 | * Set if RAM could not be initialized. This includes RAM is missing, |
| 330 | * unsupported RAM configuration, or RAM failure. |
| 331 | */ |
| 332 | #define POST_RAM_FAILURE 0xe3 |
| 333 | |
| 334 | /** |
Keith Short | 15588b0 | 2019-05-09 11:40:34 -0600 | [diff] [blame] | 335 | * \brief Hardware initialization failure |
| 336 | * |
| 337 | * Set when a required hardware component was not found or is unsupported. |
| 338 | */ |
| 339 | #define POST_HW_INIT_FAILURE 0xe4 |
| 340 | |
| 341 | /** |
Keith Short | c58e3bd | 2019-05-10 11:14:31 -0600 | [diff] [blame] | 342 | * \brief Video failure |
| 343 | * |
| 344 | * Video subsystem failed to initialize. |
| 345 | */ |
| 346 | #define POST_VIDEO_FAILURE 0xe5 |
| 347 | |
| 348 | /** |
Duncan Laurie | 4397aa1 | 2014-05-12 10:22:01 -0700 | [diff] [blame] | 349 | * \brief TPM failure |
| 350 | * |
Elyes HAOUAS | 5f73e22 | 2020-01-15 21:13:45 +0100 | [diff] [blame] | 351 | * An error with the TPM, either unexpected state or communications failure. |
Duncan Laurie | 4397aa1 | 2014-05-12 10:22:01 -0700 | [diff] [blame] | 352 | */ |
| 353 | #define POST_TPM_FAILURE 0xed |
| 354 | |
| 355 | /** |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 356 | * \brief Not supposed to get here |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 357 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 358 | * A function that should not have returned, returned |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 359 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 360 | * Check the console output for details. |
| 361 | */ |
| 362 | #define POST_DEAD_CODE 0xee |
| 363 | |
| 364 | /** |
Duncan Laurie | 727b545 | 2013-08-08 16:28:41 -0700 | [diff] [blame] | 365 | * \brief Resume from suspend failed |
| 366 | * |
| 367 | * This post code is sent when the firmware is expected to resume it is |
| 368 | * unable to do so. |
| 369 | */ |
| 370 | #define POST_RESUME_FAILURE 0xef |
| 371 | |
| 372 | /** |
Sindhoor Tilak | e5f25ce | 2020-06-19 20:46:40 -0400 | [diff] [blame] | 373 | * \brief Jumping to payload |
| 374 | * |
| 375 | * Called right before jumping to a payload. If the boot sequence stops with |
| 376 | * this code, chances are the payload freezes. |
| 377 | */ |
| 378 | #define POST_JUMPING_TO_PAYLOAD 0xf3 |
| 379 | |
| 380 | /** |
| 381 | * \brief Entry into elf boot |
| 382 | * |
| 383 | * This POST code is called right before invoking jmp_to_elf_entry() |
| 384 | * jmp_to_elf_entry() invokes the payload, and should never return |
| 385 | */ |
| 386 | #define POST_ENTER_ELF_BOOT 0xf8 |
| 387 | |
| 388 | /** |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 389 | * \brief Final code before OS resumes |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 390 | * |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 391 | * Called right before jumping to the OS resume vector. |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 392 | */ |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 393 | #define POST_OS_RESUME 0xfd |
| 394 | |
| 395 | /** |
| 396 | * \brief Final code before OS boots |
| 397 | * |
| 398 | * This may not be called depending on the payload used. |
| 399 | */ |
| 400 | #define POST_OS_BOOT 0xfe |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 401 | |
| 402 | /** |
| 403 | * \brief Elfload fail or die() called |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 404 | * |
Martin Roth | e18e642 | 2017-06-03 20:03:18 -0600 | [diff] [blame] | 405 | * coreboot was not able to load the payload, no payload was detected |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 406 | * or die() was called. |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 407 | * \n |
| 408 | * If this code appears before entering ramstage, then most likely |
| 409 | * ramstage is corrupted, and reflashing of the ROM chip is needed. |
| 410 | * \n |
| 411 | * If this code appears after ramstage, there is a problem with the payload |
| 412 | * If the payload was built out-of-tree, check that it was compiled as |
| 413 | * a coreboot payload |
| 414 | * \n |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 415 | * Check the console output to see exactly where the failure occurred. |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 416 | */ |
Lee Leahy | 84d20d0 | 2017-03-07 15:00:18 -0800 | [diff] [blame] | 417 | #define POST_DIE 0xff |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 418 | |
Martin Roth | fd277d8 | 2016-01-11 12:47:30 -0700 | [diff] [blame] | 419 | #endif /* POST_CODES_H */ |