Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com> |
| 5 | * |
| 6 | * This program is free software: you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation, either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 15 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | /** |
| 22 | * @file post_codes.h |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 23 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 24 | * This aims to be a central point for POST codes used throughout coreboot. |
| 25 | * All POST codes should be declared here as macros, and post_code() should |
| 26 | * be used with the macros instead of hardcoded values. This allows us to |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 27 | * quickly reference POST codes when nothing is working |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 28 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 29 | * The format for a POST code macro is |
| 30 | * #define POST_WHAT_WE_COMMUNICATE_IS_HAPPENING_WHEN_THIS_CODE_IS_POSTED |
| 31 | * Lets's keep it at POST_* instead of POST_CODE_* |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 32 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 33 | * This file is also included by early assembly files. Only use #define s; |
| 34 | * no function prototypes allowed here |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 35 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 36 | * DOCUMENTATION: |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 37 | * Please document any and all post codes using Doxygen style comments. We |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 38 | * want to be able to generate a verbose enough documentation that is useful |
| 39 | * during debugging. Failure to do so will result in your patch being rejected |
| 40 | * without any explanation or effort on part of the maintainers. |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 41 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 42 | */ |
| 43 | #ifndef POST_CODES_H |
| 44 | #define POST_CODES_H |
| 45 | |
| 46 | /** |
| 47 | * \brief Entry into 'crt0.s'. reset code jumps to here |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 48 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 49 | * First instruction that gets executed after the reset vector jumps. |
| 50 | * This indicates that the reset vector points to the correct code segment. |
| 51 | */ |
| 52 | #define POST_RESET_VECTOR_CORRECT 0x01 |
| 53 | |
| 54 | /** |
| 55 | * \brief Entry into protected mode |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 56 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 57 | * Preparing to enter protected mode. This is POSTed right before changing to |
| 58 | * protected mode. |
| 59 | */ |
| 60 | #define POST_ENTER_PROTECTED_MODE 0x10 |
| 61 | |
| 62 | /** |
| 63 | * \brief Start copying coreboot to RAM with decompression if compressed |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 64 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 65 | * POSTed before ramstage is about to be loaded into memory |
| 66 | */ |
| 67 | #define POST_PREPARE_RAMSTAGE 0x11 |
| 68 | |
| 69 | /** |
| 70 | * \brief Copy/decompression finished; jumping to RAM |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 71 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 72 | * This is called after ramstage is loaded in memory, and before |
| 73 | * the code jumps there. This represents the end of romstage. |
| 74 | */ |
| 75 | #define POST_RAMSTAGE_IS_PREPARED 0x12 |
| 76 | |
| 77 | |
| 78 | /** |
| 79 | * \brief Entry into c_start |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 80 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 81 | * c_start.S is the first code executing in ramstage. |
| 82 | */ |
| 83 | #define POST_ENTRY_C_START 0x13 |
| 84 | |
| 85 | /** |
Stefan Reinauer | 6adef08 | 2013-05-09 16:30:06 -0700 | [diff] [blame] | 86 | * \brief Pre call to ram stage main() |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 87 | * |
Stefan Reinauer | 6adef08 | 2013-05-09 16:30:06 -0700 | [diff] [blame] | 88 | * POSTed right before ram stage main() is called from c_start.S |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 89 | */ |
| 90 | #define POST_PRE_HARDWAREMAIN 0x79 |
| 91 | |
| 92 | /** |
Stefan Reinauer | 6adef08 | 2013-05-09 16:30:06 -0700 | [diff] [blame] | 93 | * \brief Entry into coreboot in ram stage main() |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 94 | * |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 95 | * This is the first call in hardwaremain.c. If this code is POSTed, then |
| 96 | * ramstage has successfully loaded and started executing. |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 97 | */ |
| 98 | #define POST_ENTRY_RAMSTAGE 0x80 |
| 99 | |
| 100 | /** |
| 101 | * \brief Console is initialized |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 102 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 103 | * The console is initialized and is ready for usage |
| 104 | */ |
| 105 | #define POST_CONSOLE_READY 0x39 |
| 106 | |
| 107 | /** |
| 108 | * \brief Console boot message succeeded |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 109 | * |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 110 | * First console message has been successfully sent through the console backend |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 111 | * driver. |
| 112 | */ |
| 113 | #define POST_CONSOLE_BOOT_MSG 0x40 |
| 114 | |
| 115 | /** |
Vikram Narayanan | 0713ca3 | 2012-01-23 01:44:44 +0530 | [diff] [blame] | 116 | * \brief Before enabling the cache |
| 117 | * |
| 118 | * Going to enable the cache |
| 119 | */ |
| 120 | #define POST_ENABLING_CACHE 0x60 |
| 121 | |
| 122 | /** |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame^] | 123 | * \brief Before Device Probe |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 124 | * |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame^] | 125 | * Boot State Machine: bs_pre_device() |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 126 | */ |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame^] | 127 | #define POST_BS_PRE_DEVICE 0x70 |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 128 | |
| 129 | /** |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame^] | 130 | * \brief Initializing Chips |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 131 | * |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame^] | 132 | * Boot State Machine: bs_dev_init_chips() |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 133 | */ |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame^] | 134 | #define POST_BS_DEV_INIT_CHIPS 0x71 |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 135 | |
| 136 | /** |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame^] | 137 | * \brief Starting Device Enumeration |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 138 | * |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame^] | 139 | * Boot State Machine: bs_dev_enumerate() |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 140 | */ |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame^] | 141 | #define POST_BS_DEV_ENUMERATE 0x72 |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 142 | |
| 143 | /** |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame^] | 144 | * \brief Device Resource Allocatio |
Stefan Reinauer | 52095f5 | 2012-08-07 13:14:20 -0700 | [diff] [blame] | 145 | * |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame^] | 146 | * Boot State Machine: bs_dev_resources() |
Stefan Reinauer | 52095f5 | 2012-08-07 13:14:20 -0700 | [diff] [blame] | 147 | */ |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame^] | 148 | #define POST_BS_DEV_RESOURCES 0x73 |
| 149 | |
| 150 | /** |
| 151 | * \brief Device Enable |
| 152 | * |
| 153 | * Boot State Machine: bs_dev_enable() |
| 154 | */ |
| 155 | #define POST_BS_DEV_ENABLE 0x74 |
| 156 | |
| 157 | /** |
| 158 | * \brief Device Initialization |
| 159 | * |
| 160 | * Boot State Machine: bs_dev_init() |
| 161 | */ |
| 162 | #define POST_BS_DEV_INIT 0x75 |
| 163 | |
| 164 | /** |
| 165 | * \brief After Device Probe |
| 166 | * |
| 167 | * Boot State Machine: bs_post_device() |
| 168 | */ |
| 169 | #define POST_BS_POST_DEVICE 0x76 |
| 170 | |
| 171 | /** |
| 172 | * \brief OS Resume Check |
| 173 | * |
| 174 | * Boot State Machine: bs_os_resume_check() |
| 175 | */ |
| 176 | #define POST_BS_OS_RESUME_CHECK 0x77 |
| 177 | |
| 178 | /** |
| 179 | * \brief OS Resume |
| 180 | * |
| 181 | * Boot State Machine: bs_os_resume() |
| 182 | */ |
| 183 | #define POST_BS_OS_RESUME 0x78 |
| 184 | |
| 185 | /** |
| 186 | * \brief Write Tables |
| 187 | * |
| 188 | * Boot State Machine: bs_write_tables() |
| 189 | */ |
| 190 | #define POST_BS_WRITE_TABLES 0x79 |
| 191 | |
| 192 | /** |
| 193 | * \brief Load Payload |
| 194 | * |
| 195 | * Boot State Machine: bs_payload_load() |
| 196 | */ |
| 197 | #define POST_BS_PAYLOAD_LOAD 0x7a |
| 198 | |
| 199 | /** |
| 200 | * \brief Boot Payload |
| 201 | * |
| 202 | * Boot State Machine: bs_payload_boot() |
| 203 | */ |
| 204 | #define POST_BS_PAYLOAD_BOOT 0x7b |
Stefan Reinauer | 52095f5 | 2012-08-07 13:14:20 -0700 | [diff] [blame] | 205 | |
| 206 | /** |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 207 | * \brief Entry into elf boot |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 208 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 209 | * This POST code is called right before invoking jmp_to_elf_entry() |
| 210 | * jmp_to_elf_entry() invokes the payload, and should never return |
| 211 | */ |
| 212 | #define POST_ENTER_ELF_BOOT 0xf8 |
| 213 | |
| 214 | /** |
| 215 | * \brief Jumping to payload |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 216 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 217 | * Called right before jumping to a payload. If the boot sequence stops with |
| 218 | * this code, chances are the payload freezes. |
| 219 | */ |
| 220 | #define POST_JUMPING_TO_PAYLOAD 0xf3 |
| 221 | |
| 222 | /** |
| 223 | * \brief Not supposed to get here |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 224 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 225 | * A function that should not have returned, returned |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 226 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 227 | * Check the console output for details. |
| 228 | */ |
| 229 | #define POST_DEAD_CODE 0xee |
| 230 | |
| 231 | /** |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 232 | * \brief Final code before OS resumes |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 233 | * |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 234 | * Called right before jumping to the OS resume vector. |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 235 | */ |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 236 | #define POST_OS_RESUME 0xfd |
| 237 | |
| 238 | /** |
| 239 | * \brief Final code before OS boots |
| 240 | * |
| 241 | * This may not be called depending on the payload used. |
| 242 | */ |
| 243 | #define POST_OS_BOOT 0xfe |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 244 | |
| 245 | /** |
| 246 | * \brief Elfload fail or die() called |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 247 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 248 | * Coreboot was not able to load the payload, no payload was detected |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 249 | * or die() was called. |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 250 | * \n |
| 251 | * If this code appears before entering ramstage, then most likely |
| 252 | * ramstage is corrupted, and reflashing of the ROM chip is needed. |
| 253 | * \n |
| 254 | * If this code appears after ramstage, there is a problem with the payload |
| 255 | * If the payload was built out-of-tree, check that it was compiled as |
| 256 | * a coreboot payload |
| 257 | * \n |
| 258 | * Check the console output to see exactly where the failure occured. |
| 259 | */ |
| 260 | #define POST_DIE 0xff |
| 261 | |
| 262 | |
| 263 | /* |
| 264 | * The following POST codes are taken from src/include/cpu/amd/geode_post_code.h |
| 265 | * They overlap with previous codes, and most are not even used |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 266 | * Some mainboards still require them, but they are deprecated. We want to consolidate |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 267 | * our own POST code structure with the codes above. |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 268 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 269 | * standard AMD post definitions for the AMD Geode |
| 270 | */ |
| 271 | #define POST_Output_Port (0x080) /* port to write post codes to*/ |
| 272 | |
| 273 | #define POST_preSioInit (0x000) |
| 274 | #define POST_clockInit (0x001) |
| 275 | #define POST_CPURegInit (0x002) |
| 276 | #define POST_UNREAL (0x003) |
| 277 | #define POST_CPUMemRegInit (0x004) |
| 278 | #define POST_CPUTest (0x005) |
| 279 | #define POST_memSetup (0x006) |
| 280 | #define POST_memSetUpStack (0x007) |
| 281 | #define POST_memTest (0x008) |
| 282 | #define POST_shadowRom (0x009) |
| 283 | #define POST_memRAMoptimize (0x00A) |
| 284 | #define POST_cacheInit (0x00B) |
| 285 | #define POST_northBridgeInit (0x00C) |
| 286 | #define POST_chipsetInit (0x00D) |
| 287 | #define POST_sioTest (0x00E) |
| 288 | #define POST_pcATjunk (0x00F) |
| 289 | |
| 290 | #define POST_intTable (0x010) |
| 291 | #define POST_memInfo (0x011) |
| 292 | #define POST_romCopy (0x012) |
| 293 | #define POST_PLLCheck (0x013) |
| 294 | #define POST_keyboardInit (0x014) |
| 295 | #define POST_cpuCacheOff (0x015) |
| 296 | #define POST_BDAInit (0x016) |
| 297 | #define POST_pciScan (0x017) |
| 298 | #define POST_optionRomInit (0x018) |
| 299 | #define POST_ResetLimits (0x019) |
| 300 | #define POST_summary_screen (0x01A) |
| 301 | #define POST_Boot (0x01B) |
| 302 | #define POST_SystemPreInit (0x01C) |
| 303 | #define POST_ClearRebootFlag (0x01D) |
| 304 | #define POST_GLIUInit (0x01E) |
| 305 | #define POST_BootFailed (0x01F) |
| 306 | |
| 307 | #define POST_CPU_ID (0x020) |
| 308 | #define POST_COUNTERBROKEN (0x021) |
| 309 | #define POST_DIFF_DIMMS (0x022) |
| 310 | #define POST_WIGGLE_MEM_LINES (0x023) |
| 311 | #define POST_NO_GLIU_DESC (0x024) |
| 312 | #define POST_CPU_LCD_CHECK (0x025) |
| 313 | #define POST_CPU_LCD_PASS (0x026) |
| 314 | #define POST_CPU_LCD_FAIL (0x027) |
| 315 | #define POST_CPU_STEPPING (0x028) |
| 316 | #define POST_CPU_DM_BIST_FAILURE (0x029) |
| 317 | #define POST_CPU_FLAGS (0x02A) |
| 318 | #define POST_CHIPSET_ID (0x02B) |
| 319 | #define POST_CHIPSET_ID_PASS (0x02C) |
| 320 | #define POST_CHIPSET_ID_FAIL (0x02D) |
| 321 | #define POST_CPU_ID_GOOD (0x02E) |
| 322 | #define POST_CPU_ID_FAIL (0x02F) |
| 323 | |
| 324 | /* PCI config*/ |
| 325 | #define P80_PCICFG (0x030) |
| 326 | |
| 327 | /* PCI io*/ |
| 328 | #define P80_PCIIO (0x040) |
| 329 | |
| 330 | /* PCI memory*/ |
| 331 | #define P80_PCIMEM (0x050) |
| 332 | |
| 333 | /* SIO*/ |
| 334 | #define P80_SIO (0x060) |
| 335 | |
| 336 | /* Memory Setp*/ |
| 337 | #define P80_MEM_SETUP (0x070) |
| 338 | #define POST_MEM_SETUP (0x070) |
| 339 | #define ERROR_32BIT_DIMMS (0x071) |
| 340 | #define POST_MEM_SETUP2 (0x072) |
| 341 | #define POST_MEM_SETUP3 (0x073) |
| 342 | #define POST_MEM_SETUP4 (0x074) |
| 343 | #define POST_MEM_SETUP5 (0x075) |
| 344 | #define POST_MEM_ENABLE (0x076) |
| 345 | #define ERROR_NO_DIMMS (0x077) |
| 346 | #define ERROR_DIFF_DIMMS (0x078) |
| 347 | #define ERROR_BAD_LATENCY (0x079) |
| 348 | #define ERROR_SET_PAGE (0x07A) |
| 349 | #define ERROR_DENSITY_DIMM (0x07B) |
| 350 | #define ERROR_UNSUPPORTED_DIMM (0x07C) |
| 351 | #define ERROR_BANK_SET (0x07D) |
| 352 | #define POST_MEM_SETUP_GOOD (0x07E) |
| 353 | #define POST_MEM_SETUP_FAIL (0x07F) |
| 354 | |
| 355 | #define POST_UserPreInit (0x080) |
| 356 | #define POST_UserPostInit (0x081) |
| 357 | #define POST_Equipment_check (0x082) |
| 358 | #define POST_InitNVRAMBX (0x083) |
| 359 | #define POST_NoPIRTable (0x084) |
| 360 | #define POST_ChipsetFingerPrintPass (0x085) |
| 361 | #define POST_ChipsetFingerPrintFail (0x086) |
| 362 | #define POST_CPU_IM_TAG_BIST_FAILURE (0x087) |
| 363 | #define POST_CPU_IM_DATA_BIST_FAILURE (0x088) |
| 364 | #define POST_CPU_FPU_BIST_FAILURE (0x089) |
| 365 | #define POST_CPU_BTB_BIST_FAILURE (0x08A) |
| 366 | #define POST_CPU_EX_BIST_FAILURE (0x08B) |
| 367 | #define POST_Chipset_PI_Test_Fail (0x08C) |
| 368 | #define POST_Chipset_SMBus_SDA_Test_Fail (0x08D) |
| 369 | #define POST_BIT_CLK_Fail (0x08E) |
| 370 | |
| 371 | #define POST_STACK_SETUP (0x090) |
| 372 | #define POST_CPU_PF_BIST_FAILURE (0x091) |
| 373 | #define POST_CPU_L2_BIST_FAILURE (0x092) |
| 374 | #define POST_CPU_GLCP_BIST_FAILURE (0x093) |
| 375 | #define POST_CPU_DF_BIST_FAILURE (0x094) |
| 376 | #define POST_CPU_VG_BIST_FAILURE (0x095) |
| 377 | #define POST_CPU_VIP_BIST_FAILURE (0x096) |
| 378 | #define POST_STACK_SETUP_PASS (0x09E) |
| 379 | #define POST_STACK_SETUP_FAIL (0x09F) |
| 380 | |
| 381 | #define POST_PLL_INIT (0x0A0) |
| 382 | #define POST_PLL_MANUAL (0x0A1) |
| 383 | #define POST_PLL_STRAP (0x0A2) |
| 384 | #define POST_PLL_RESET_FAIL (0x0A3) |
| 385 | #define POST_PLL_PCI_FAIL (0x0A4) |
| 386 | #define POST_PLL_MEM_FAIL (0x0A5) |
| 387 | #define POST_PLL_CPU_VER_FAIL (0x0A6) |
| 388 | |
| 389 | #define POST_MEM_TESTMEM (0x0B0) |
| 390 | #define POST_MEM_TESTMEM1 (0x0B1) |
| 391 | #define POST_MEM_TESTMEM2 (0x0B2) |
| 392 | #define POST_MEM_TESTMEM3 (0x0B3) |
| 393 | #define POST_MEM_TESTMEM4 (0x0B4) |
| 394 | #define POST_MEM_TESTMEM_PASS (0x0BE) |
| 395 | #define POST_MEM_TESTMEM_FAIL (0x0BF) |
| 396 | |
| 397 | #define POST_SECUROM_SECBOOT_START (0x0C0) |
| 398 | #define POST_SECUROM_BOOTSRCSETUP (0x0C1) |
| 399 | #define POST_SECUROM_REMAP_FAIL (0x0C2) |
| 400 | #define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) |
| 401 | #define POST_SECUROM_DCACHESETUP (0x0C4) |
| 402 | #define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) |
| 403 | #define POST_SECUROM_ICACHESETUP (0x0C6) |
| 404 | #define POST_SECUROM_DESCRIPTORSETUP (0x0C7) |
| 405 | #define POST_SECUROM_DCACHESETUPBIOS (0x0C8) |
| 406 | #define POST_SECUROM_PLATFORMSETUP (0x0C9) |
| 407 | #define POST_SECUROM_SIGCHECKBIOS (0x0CA) |
| 408 | #define POST_SECUROM_ICACHESETUPBIOS (0x0CB) |
| 409 | #define POST_SECUROM_PASS (0x0CC) |
| 410 | #define POST_SECUROM_FAIL (0x0CD) |
| 411 | |
| 412 | #define POST_RCONFInitError (0x0CE) |
| 413 | #define POST_CacheInitError (0x0CF) |
| 414 | |
| 415 | #define POST_ROM_PREUNCOMPRESS (0x0D0) |
| 416 | #define POST_ROM_UNCOMPRESS (0x0D1) |
| 417 | #define POST_ROM_SMM_INIT (0x0D2) |
| 418 | #define POST_ROM_VID_BIOS (0x0D3) |
| 419 | #define POST_ROM_LCDINIT (0x0D4) |
| 420 | #define POST_ROM_SPLASH (0x0D5) |
| 421 | #define POST_ROM_HDDINIT (0x0D6) |
| 422 | #define POST_ROM_SYS_INIT (0x0D7) |
| 423 | #define POST_ROM_DMM_INIT (0x0D8) |
| 424 | #define POST_ROM_TVINIT (0x0D9) |
| 425 | #define POST_ROM_POSTUNCOMPRESS (0x0DE) |
| 426 | |
| 427 | #define P80_CHIPSET_INIT (0x0E0) |
| 428 | #define POST_PreChipsetInit (0x0E1) |
| 429 | #define POST_LateChipsetInit (0x0E2) |
| 430 | #define POST_NORTHB_INIT (0x0E8) |
| 431 | |
| 432 | #define POST_INTR_SEG_JUMP (0x0F0) |
| 433 | |
| 434 | #endif /* THE_ALMIGHTY_POST_CODES_H */ |