Lee Leahy | ce9e21a | 2016-06-05 18:48:31 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2015-2016 Intel Corp. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | #include <bootblock_common.h> |
| 17 | #include <console/console.h> |
| 18 | #include <device/pci_def.h> |
| 19 | #include <program_loading.h> |
| 20 | #include <soc/iomap.h> |
Lee Leahy | 3d0e3cf | 2016-07-25 07:11:05 -0700 | [diff] [blame] | 21 | #include <soc/intel/common/util.h> |
Lee Leahy | ce9e21a | 2016-06-05 18:48:31 -0700 | [diff] [blame] | 22 | #include <soc/pci_devs.h> |
| 23 | #include <soc/reg_access.h> |
| 24 | |
Lee Leahy | a765090 | 2016-12-28 11:43:10 -0800 | [diff] [blame] | 25 | extern void asmlinkage light_sd_led(void); |
| 26 | |
Lee Leahy | ce9e21a | 2016-06-05 18:48:31 -0700 | [diff] [blame] | 27 | static const struct reg_script legacy_gpio_init[] = { |
| 28 | /* Temporarily enable the legacy GPIO controller */ |
| 29 | REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID |
| 30 | | LEGACY_GPIO_BASE_ADDRESS), |
| 31 | /* Temporarily enable the GPE controller */ |
| 32 | REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID |
| 33 | | GPE0_BASE_ADDRESS), |
| 34 | REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO), |
| 35 | REG_SCRIPT_END |
| 36 | }; |
| 37 | |
| 38 | static const struct reg_script i2c_gpio_controller_init[] = { |
| 39 | /* Temporarily enable the GPIO controller */ |
| 40 | REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), |
| 41 | REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), |
| 42 | REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), |
| 43 | REG_SCRIPT_END |
| 44 | }; |
| 45 | |
| 46 | static const struct reg_script hsuart_init[] = { |
| 47 | /* Enable the HSUART */ |
| 48 | REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS), |
| 49 | REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), |
| 50 | REG_SCRIPT_END |
| 51 | }; |
| 52 | |
Lee Leahy | 3d0e3cf | 2016-07-25 07:11:05 -0700 | [diff] [blame] | 53 | static const struct reg_script mtrr_init[] = { |
| 54 | /* Use write-through caching, for FSP 2.0 the cache will be invalidated |
| 55 | * postchar (arch/x86/exit_car.S). |
| 56 | */ |
| 57 | |
| 58 | /* Enable the cache */ |
| 59 | REG_CPU_CR_AND(0, ~(CR0_CD | CR0_NW)), |
| 60 | |
| 61 | /* Cache the SPI flash */ |
| 62 | REG_MSR_WRITE(MTRR_PHYS_BASE(0), (uint32_t)((-CONFIG_ROM_SIZE) |
| 63 | | MTRR_TYPE_WRTHROUGH)), |
| 64 | REG_MSR_WRITE(MTRR_PHYS_MASK(0), (uint32_t)((-CONFIG_ROM_SIZE) |
| 65 | | MTRR_PHYS_MASK_VALID)), |
| 66 | |
| 67 | /* Cache ESRAM */ |
| 68 | REG_MSR_WRITE(MTRR_PHYS_BASE(1), (uint32_t)(0x80000000 |
| 69 | | MTRR_TYPE_WRTHROUGH)), |
| 70 | REG_MSR_WRITE(MTRR_PHYS_MASK(1), (uint32_t)((~0x7ffff) |
| 71 | | MTRR_PHYS_MASK_VALID)), |
| 72 | |
| 73 | /* Enable the variable MTRRs */ |
| 74 | REG_MSR_WRITE(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_EN |
| 75 | | MTRR_TYPE_UNCACHEABLE), |
| 76 | |
| 77 | REG_SCRIPT_END |
| 78 | }; |
| 79 | |
Lee Leahy | 3de7d4a | 2016-08-02 17:35:22 -0700 | [diff] [blame] | 80 | void asmlinkage bootblock_c_entry(uint64_t base_timestamp) |
| 81 | { |
Lee Leahy | a765090 | 2016-12-28 11:43:10 -0800 | [diff] [blame] | 82 | if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY)) |
| 83 | light_sd_led(); |
| 84 | |
Lee Leahy | 3de7d4a | 2016-08-02 17:35:22 -0700 | [diff] [blame] | 85 | bootblock_main_with_timestamp(base_timestamp); |
| 86 | } |
| 87 | |
Lee Leahy | ce9e21a | 2016-06-05 18:48:31 -0700 | [diff] [blame] | 88 | void bootblock_soc_early_init(void) |
| 89 | { |
Lee Leahy | a765090 | 2016-12-28 11:43:10 -0800 | [diff] [blame] | 90 | if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY)) |
| 91 | light_sd_led(); |
| 92 | |
Lee Leahy | 3d0e3cf | 2016-07-25 07:11:05 -0700 | [diff] [blame] | 93 | /* Initialize the MTRRs */ |
| 94 | reg_script_run(mtrr_init); |
| 95 | |
Lee Leahy | ce9e21a | 2016-06-05 18:48:31 -0700 | [diff] [blame] | 96 | /* Initialize the controllers */ |
| 97 | reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); |
| 98 | reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); |
| 99 | |
| 100 | /* Enable the HSUART */ |
| 101 | if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) |
| 102 | reg_script_run_on_dev(HSUART0_BDF, hsuart_init); |
| 103 | if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) |
| 104 | reg_script_run_on_dev(HSUART1_BDF, hsuart_init); |
Lee Leahy | a765090 | 2016-12-28 11:43:10 -0800 | [diff] [blame] | 105 | |
| 106 | if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT)) |
| 107 | light_sd_led(); |
Lee Leahy | ce9e21a | 2016-06-05 18:48:31 -0700 | [diff] [blame] | 108 | } |
| 109 | |
Lee Leahy | 3d0e3cf | 2016-07-25 07:11:05 -0700 | [diff] [blame] | 110 | void bootblock_soc_init(void) |
| 111 | { |
Lee Leahy | a765090 | 2016-12-28 11:43:10 -0800 | [diff] [blame] | 112 | if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_INIT_ENTRY)) |
| 113 | light_sd_led(); |
| 114 | |
Lee Leahy | 3d0e3cf | 2016-07-25 07:11:05 -0700 | [diff] [blame] | 115 | /* Display the MTRRs */ |
| 116 | soc_display_mtrrs(); |
| 117 | } |
| 118 | |
Lee Leahy | ce9e21a | 2016-06-05 18:48:31 -0700 | [diff] [blame] | 119 | void platform_prog_run(struct prog *prog) |
| 120 | { |
| 121 | /* Display the program entry point */ |
| 122 | printk(BIOS_SPEW, "Calling %s, 0x%p(0x%p)\n", prog->name, |
| 123 | prog->entry, prog->arg); |
| 124 | } |