commit 3d0e3cf4b125dfda236d6978adea5f5d40fd78e8
author Lee Leahy <leroy.p.leahy@intel.com> Mon Jul 25 07:11:05 2016 -0700
committer Lee Leahy <leroy.p.leahy@intel.com> Wed Aug 03 17:46:36 2016 +0200
tree f0b83e01591f3eb34084ad038cf45e1ea4cc7760
parent 14d09264a2b64c38bf4e5cf309947a8a2fbafc6d

soc/intel/quark: Initialize MTRRs in bootblock

Initialize the MTRRs for use by bootblock and romstage.
Display the MTRRs.

TEST=Build and run on Galileo Gen2.

Change-Id: Ib1d422c738820163f54771c65034ae77301237ec
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15861
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/intel/quark/bootblock/bootblock.c

diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c
index 4aa774b..959084d 100644
--- a/src/soc/intel/quark/bootblock/bootblock.c
+++ b/src/soc/intel/quark/bootblock/bootblock.c
@@ -18,6 +18,7 @@
 #include <device/pci_def.h>
 #include <program_loading.h>
 #include <soc/iomap.h>
+#include <soc/intel/common/util.h>
 #include <soc/pci_devs.h>
 #include <soc/reg_access.h>
 
@@ -47,8 +48,38 @@
 	REG_SCRIPT_END
 };
 
+static const struct reg_script mtrr_init[] = {
+	/* Use write-through caching, for FSP 2.0 the cache will be invalidated
+	 * postchar (arch/x86/exit_car.S).
+	 */
+
+	/* Enable the cache */
+	REG_CPU_CR_AND(0, ~(CR0_CD | CR0_NW)),
+
+	/* Cache the SPI flash */
+	REG_MSR_WRITE(MTRR_PHYS_BASE(0), (uint32_t)((-CONFIG_ROM_SIZE)
+		| MTRR_TYPE_WRTHROUGH)),
+	REG_MSR_WRITE(MTRR_PHYS_MASK(0), (uint32_t)((-CONFIG_ROM_SIZE)
+		| MTRR_PHYS_MASK_VALID)),
+
+	/* Cache ESRAM */
+	REG_MSR_WRITE(MTRR_PHYS_BASE(1), (uint32_t)(0x80000000
+		| MTRR_TYPE_WRTHROUGH)),
+	REG_MSR_WRITE(MTRR_PHYS_MASK(1), (uint32_t)((~0x7ffff)
+		| MTRR_PHYS_MASK_VALID)),
+
+	/* Enable the variable MTRRs */
+	REG_MSR_WRITE(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_EN
+		| MTRR_TYPE_UNCACHEABLE),
+
+	REG_SCRIPT_END
+};
+
 void bootblock_soc_early_init(void)
 {
+	/* Initialize the MTRRs */
+	reg_script_run(mtrr_init);
+
 	/* Initialize the controllers */
 	reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
 	reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
@@ -60,6 +91,12 @@
 		reg_script_run_on_dev(HSUART1_BDF, hsuart_init);
 }
 
+void bootblock_soc_init(void)
+{
+	/* Display the MTRRs */
+	soc_display_mtrrs();
+}
+
 void platform_prog_run(struct prog *prog)
 {
 	/* Display the program entry point */