Lee Leahy | ce9e21a | 2016-06-05 18:48:31 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2015-2016 Intel Corp. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | #include <bootblock_common.h> |
| 17 | #include <console/console.h> |
| 18 | #include <device/pci_def.h> |
| 19 | #include <program_loading.h> |
| 20 | #include <soc/iomap.h> |
| 21 | #include <soc/pci_devs.h> |
| 22 | #include <soc/reg_access.h> |
| 23 | |
| 24 | static const struct reg_script clear_smi_and_wake_events[] = { |
| 25 | /* Clear any SMI or wake events */ |
| 26 | REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S), |
| 27 | REG_GPE0_READ(R_QNC_GPE0BLK_SMIS), |
| 28 | REG_GPE0_OR(R_QNC_GPE0BLK_GPE0S, B_QNC_GPE0BLK_GPE0S_ALL), |
| 29 | REG_GPE0_OR(R_QNC_GPE0BLK_SMIS, B_QNC_GPE0BLK_SMIS_ALL), |
| 30 | REG_SCRIPT_END |
| 31 | }; |
| 32 | |
| 33 | static const struct reg_script legacy_gpio_init[] = { |
| 34 | /* Temporarily enable the legacy GPIO controller */ |
| 35 | REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID |
| 36 | | LEGACY_GPIO_BASE_ADDRESS), |
| 37 | /* Temporarily enable the GPE controller */ |
| 38 | REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID |
| 39 | | GPE0_BASE_ADDRESS), |
| 40 | REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO), |
| 41 | REG_SCRIPT_END |
| 42 | }; |
| 43 | |
| 44 | static const struct reg_script i2c_gpio_controller_init[] = { |
| 45 | /* Temporarily enable the GPIO controller */ |
| 46 | REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), |
| 47 | REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), |
| 48 | REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), |
| 49 | REG_SCRIPT_END |
| 50 | }; |
| 51 | |
| 52 | static const struct reg_script hsuart_init[] = { |
| 53 | /* Enable the HSUART */ |
| 54 | REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS), |
| 55 | REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), |
| 56 | REG_SCRIPT_END |
| 57 | }; |
| 58 | |
| 59 | void bootblock_soc_early_init(void) |
| 60 | { |
| 61 | /* Initialize the controllers */ |
| 62 | reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); |
| 63 | reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); |
| 64 | |
| 65 | /* Enable the HSUART */ |
| 66 | if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) |
| 67 | reg_script_run_on_dev(HSUART0_BDF, hsuart_init); |
| 68 | if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) |
| 69 | reg_script_run_on_dev(HSUART1_BDF, hsuart_init); |
| 70 | } |
| 71 | |
| 72 | void platform_prog_run(struct prog *prog) |
| 73 | { |
| 74 | /* Display the program entry point */ |
| 75 | printk(BIOS_SPEW, "Calling %s, 0x%p(0x%p)\n", prog->name, |
| 76 | prog->entry, prog->arg); |
| 77 | } |