blob: bb6e22cb739463da86a9645a5db9760d4d6a3026 [file] [log] [blame]
Vladimir Serbinenko888d5592013-11-13 17:53:38 +01001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2011 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Vladimir Serbinenko888d5592013-11-13 17:53:38 +010015
16config SOUTHBRIDGE_INTEL_IBEXPEAK
17 bool
18
19if SOUTHBRIDGE_INTEL_IBEXPEAK
20
21config SOUTH_BRIDGE_OPTIONS # dummy
22 def_bool y
Aaron Durbin78c68432016-07-13 23:23:54 -050023 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Vladimir Serbinenko888d5592013-11-13 17:53:38 +010024 select IOAPIC
Vladimir Serbinenko888d5592013-11-13 17:53:38 +010025 select HAVE_USBDEBUG
26 select HAVE_SMI_HANDLER
27 select USE_WATCHDOG_ON_BOOT
28 select PCIEXP_ASPM
29 select PCIEXP_COMMON_CLOCK
Vladimir Serbinenko888d5592013-11-13 17:53:38 +010030 select SOUTHBRIDGE_INTEL_COMMON
Tristan Corrick63626b12018-11-30 22:53:50 +130031 select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
Kyösti Mälkki90993952018-05-01 19:36:25 +030032 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
Arthur Heymans16fe7902017-04-12 17:01:31 +020033 select SOUTHBRIDGE_INTEL_COMMON_SMBUS
Arthur Heymansbddef0d2017-09-25 12:21:07 +020034 select SOUTHBRIDGE_INTEL_COMMON_SPI
Vladimir Serbinenkof55f51a2013-11-25 23:40:01 +010035 select HAVE_USBDEBUG_OPTIONS
Vladimir Serbinenko67bfbfd2014-10-25 15:49:23 +020036 select COMMON_FADT
Alexander Couzensbeb31d02015-04-16 02:23:00 +020037 select ACPI_SATA_GENERATOR
Stefan Tauneref8b9572018-09-06 00:34:28 +020038 select INTEL_DESCRIPTOR_MODE_CAPABLE
Patrick Rudolph10104682016-02-06 18:12:28 +010039 select SOUTHBRIDGE_INTEL_COMMON_GPIO
Bill XIEd533b162017-08-22 16:26:22 +080040 select HAVE_INTEL_CHIPSET_LOCKDOWN
Nico Huber9faae2b2018-11-14 00:00:35 +010041 select HAVE_POWER_STATE_AFTER_FAILURE
42 select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
Vladimir Serbinenko888d5592013-11-13 17:53:38 +010043
44config EHCI_BAR
45 hex
46 default 0xfef00000
47
Vladimir Serbinenko6a7aeb32014-01-05 11:37:32 +010048config DRAM_RESET_GATE_GPIO
49 int
50 default 60
51
Vladimir Serbinenko888d5592013-11-13 17:53:38 +010052config BOOTBLOCK_SOUTHBRIDGE_INIT
53 string
54 default "southbridge/intel/bd82x6x/bootblock.c"
55
56config SERIRQ_CONTINUOUS_MODE
57 bool
58 default n
59 help
60 If you set this option to y, the serial IRQ machine will be
61 operated in continuous mode.
62
Vladimir Serbinenko888d5592013-11-13 17:53:38 +010063config HPET_MIN_TICKS
64 hex
65 default 0x80
66
Vladimir Serbinenko888d5592013-11-13 17:53:38 +010067endif