Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame^] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2011 Google Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
| 17 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | ## |
| 19 | |
| 20 | config SOUTHBRIDGE_INTEL_IBEXPEAK |
| 21 | bool |
| 22 | |
| 23 | if SOUTHBRIDGE_INTEL_IBEXPEAK |
| 24 | |
| 25 | config SOUTH_BRIDGE_OPTIONS # dummy |
| 26 | def_bool y |
| 27 | select IOAPIC |
| 28 | select HAVE_HARD_RESET |
| 29 | select HAVE_USBDEBUG |
| 30 | select HAVE_SMI_HANDLER |
| 31 | select USE_WATCHDOG_ON_BOOT |
| 32 | select PCIEXP_ASPM |
| 33 | select PCIEXP_COMMON_CLOCK |
| 34 | select SPI_FLASH |
| 35 | select SOUTHBRIDGE_INTEL_COMMON |
| 36 | |
| 37 | config EHCI_BAR |
| 38 | hex |
| 39 | default 0xfef00000 |
| 40 | |
| 41 | config EHCI_DEBUG_OFFSET |
| 42 | hex |
| 43 | default 0xa0 |
| 44 | |
| 45 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 46 | string |
| 47 | default "southbridge/intel/bd82x6x/bootblock.c" |
| 48 | |
| 49 | config SERIRQ_CONTINUOUS_MODE |
| 50 | bool |
| 51 | default n |
| 52 | help |
| 53 | If you set this option to y, the serial IRQ machine will be |
| 54 | operated in continuous mode. |
| 55 | |
| 56 | config BUILD_WITH_FAKE_IFD |
| 57 | bool "Build with a fake IFD" |
| 58 | default y if !HAVE_IFD_BIN |
| 59 | help |
| 60 | If you don't have an Intel Firmware Descriptor (ifd.bin) for your |
| 61 | board, you can select this option and coreboot will build without it. |
| 62 | Though, the resulting coreboot.rom will not contain all parts required |
| 63 | to get coreboot running on your board. You can however write only the |
| 64 | BIOS section to your board's flash ROM and keep the other sections |
| 65 | untouched. Unfortunately the current version of flashrom doesn't |
| 66 | support this yet. But there is a patch pending [1]. |
| 67 | |
| 68 | WARNING: Never write a complete coreboot.rom to your flash ROM if it |
| 69 | was built with a fake IFD. It just won't work. |
| 70 | |
| 71 | [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html |
| 72 | |
| 73 | |
| 74 | config IFD_BIOS_SECTION |
| 75 | depends on BUILD_WITH_FAKE_IFD |
| 76 | string |
| 77 | default "" |
| 78 | |
| 79 | config IFD_ME_SECTION |
| 80 | depends on BUILD_WITH_FAKE_IFD |
| 81 | string |
| 82 | default "" |
| 83 | |
| 84 | config IFD_BIN_PATH |
| 85 | string "Path to intel firmware descriptor" |
| 86 | depends on !BUILD_WITH_FAKE_IFD |
| 87 | default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" |
| 88 | |
| 89 | |
| 90 | config HAVE_ME_BIN |
| 91 | bool "Add Intel Management Engine firmware" |
| 92 | default n |
| 93 | help |
| 94 | The Intel processor in the selected system requires a special firmware |
| 95 | for an integrated controller called Management Engine (ME). The ME |
| 96 | firmware might be provided in coreboot's 3rdparty repository. If |
| 97 | not and if you don't have the firmware elsewhere, you can still |
| 98 | build coreboot without it. In this case however, you'll have to make |
| 99 | sure that you don't overwrite your ME firmware on your flash ROM. |
| 100 | |
| 101 | config ME_BIN_PATH |
| 102 | string "Path to management engine firmware" |
| 103 | depends on HAVE_ME_BIN |
| 104 | default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" |
| 105 | |
| 106 | config HPET_MIN_TICKS |
| 107 | hex |
| 108 | default 0x80 |
| 109 | |
| 110 | config LOCK_MANAGEMENT_ENGINE |
| 111 | bool "Lock Management Engine section" |
| 112 | default n |
| 113 | help |
| 114 | The Intel Management Engine supports preventing write accesses |
| 115 | from the host to the Management Engine section in the firmware |
| 116 | descriptor. If the ME section is locked, it can only be overwritten |
| 117 | with an external SPI flash programmer. You will want this if you |
| 118 | want to increase security of your ROM image once you are sure |
| 119 | that the ME firmware is no longer going to change. |
| 120 | |
| 121 | If unsure, say N. |
| 122 | |
| 123 | endif |