Angel Pons | f5627e8 | 2020-04-05 15:46:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 2 | |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 3 | #include <device/pci_ids.h> |
| 4 | #include <device/pci_ops.h> |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 5 | #include <fsp/api.h> |
| 6 | #include <soc/ramstage.h> |
| 7 | #include <soc/vr_config.h> |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 8 | #include <console/console.h> |
| 9 | #include <intelblocks/cpulib.h> |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 10 | |
| 11 | static const struct vr_config default_configs[NUM_VR_DOMAINS] = { |
Roy Mingi Park | 1ac2ad0 | 2019-02-13 11:10:45 -0800 | [diff] [blame] | 12 | [VR_SYSTEM_AGENT] = { |
| 13 | .vr_config_enable = 1, |
| 14 | .psi1threshold = VR_CFG_AMP(20), |
| 15 | .psi2threshold = VR_CFG_AMP(5), |
| 16 | .psi3threshold = VR_CFG_AMP(1), |
| 17 | .psi3enable = 1, |
| 18 | .psi4enable = 1, |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 19 | .imon_slope = 0, |
| 20 | .imon_offset = 0, |
| 21 | .icc_max = 0, |
Roy Mingi Park | 1ac2ad0 | 2019-02-13 11:10:45 -0800 | [diff] [blame] | 22 | .voltage_limit = 1520, |
| 23 | }, |
| 24 | [VR_IA_CORE] = { |
| 25 | .vr_config_enable = 1, |
| 26 | .psi1threshold = VR_CFG_AMP(20), |
| 27 | .psi2threshold = VR_CFG_AMP(5), |
| 28 | .psi3threshold = VR_CFG_AMP(1), |
| 29 | .psi3enable = 1, |
| 30 | .psi4enable = 1, |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 31 | .imon_slope = 0, |
| 32 | .imon_offset = 0, |
| 33 | .icc_max = 0, |
Roy Mingi Park | 1ac2ad0 | 2019-02-13 11:10:45 -0800 | [diff] [blame] | 34 | .voltage_limit = 1520, |
| 35 | }, |
| 36 | [VR_GT_UNSLICED] = { |
| 37 | .vr_config_enable = 1, |
| 38 | .psi1threshold = VR_CFG_AMP(20), |
| 39 | .psi2threshold = VR_CFG_AMP(5), |
| 40 | .psi3threshold = VR_CFG_AMP(1), |
| 41 | .psi3enable = 1, |
| 42 | .psi4enable = 1, |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 43 | .imon_slope = 0, |
| 44 | .imon_offset = 0, |
| 45 | .icc_max = 0, |
Roy Mingi Park | 1ac2ad0 | 2019-02-13 11:10:45 -0800 | [diff] [blame] | 46 | .voltage_limit = 1520, |
| 47 | }, |
| 48 | [VR_GT_SLICED] = { |
| 49 | .vr_config_enable = 1, |
| 50 | .psi1threshold = VR_CFG_AMP(20), |
| 51 | .psi2threshold = VR_CFG_AMP(5), |
| 52 | .psi3threshold = VR_CFG_AMP(1), |
| 53 | .psi3enable = 1, |
| 54 | .psi4enable = 1, |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 55 | .imon_slope = 0, |
| 56 | .imon_offset = 0, |
| 57 | .icc_max = 0, |
Roy Mingi Park | 1ac2ad0 | 2019-02-13 11:10:45 -0800 | [diff] [blame] | 58 | .voltage_limit = 1520, |
| 59 | }, |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 60 | }; |
| 61 | |
Patrick Rudolph | 9de8c80 | 2020-05-18 12:03:52 +0200 | [diff] [blame^] | 62 | struct vr_lookup_item { |
| 63 | uint16_t tdp_min; |
| 64 | enum chip_pl2_4_cfg pl2_4_cfg; /* Use 'value_not_set' for don't care */ |
| 65 | uint16_t conf[NUM_VR_DOMAINS]; |
| 66 | }; |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 67 | |
Patrick Rudolph | 9de8c80 | 2020-05-18 12:03:52 +0200 | [diff] [blame^] | 68 | struct vr_lookup { |
| 69 | uint16_t mchid; |
| 70 | uint8_t num_items; |
| 71 | const struct vr_lookup_item *items; |
| 72 | }; |
| 73 | |
| 74 | #define VR_CONFIG(x, y) \ |
| 75 | static const struct vr_lookup_item vr_config_##x##_##y[] = |
| 76 | #define VR_CONFIG_ICC(x) VR_CONFIG(x, ICC) |
| 77 | #define VR_CONFIG_LL(x) VR_CONFIG(x, LL) |
| 78 | #define VR_CONFIG_TDC(x) VR_CONFIG(x, TDC) |
| 79 | |
| 80 | #define VR_REFITEM(x, y) { x, ARRAY_SIZE(vr_config_##x##_##y), vr_config_##x##_##y} |
| 81 | #define VR_REFITEM_ICC(x) VR_REFITEM(x, ICC) |
| 82 | #define VR_REFITEM_LL(x) VR_REFITEM(x, LL) |
| 83 | #define VR_REFITEM_TDC(x) VR_REFITEM(x, TDC) |
| 84 | |
| 85 | static uint16_t load_table(const struct vr_lookup *tbl, |
| 86 | const int tbl_entries, |
| 87 | const int domain, |
| 88 | const uint16_t tdp, |
| 89 | const uint16_t mch_id) |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 90 | { |
Patrick Rudolph | 9de8c80 | 2020-05-18 12:03:52 +0200 | [diff] [blame^] | 91 | const config_t *cfg = config_of_soc(); |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 92 | |
Patrick Rudolph | 9de8c80 | 2020-05-18 12:03:52 +0200 | [diff] [blame^] | 93 | for (size_t i = 0; i < tbl_entries; i++) { |
| 94 | if (tbl[i].mchid != mch_id) |
| 95 | continue; |
| 96 | |
| 97 | for (size_t j = 0; j < tbl[i].num_items; j++) { |
| 98 | if (tbl[i].items[j].tdp_min > tdp) |
| 99 | continue; |
| 100 | |
| 101 | if ((tbl[i].items[j].pl2_4_cfg != value_not_set) && |
| 102 | (tbl[i].items[j].pl2_4_cfg != cfg->cpu_pl2_4_cfg)) |
| 103 | continue; |
| 104 | |
| 105 | return tbl[i].items[j].conf[domain]; |
| 106 | } |
| 107 | break; |
| 108 | } |
| 109 | |
| 110 | printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in %s\n", mch_id, __func__); |
| 111 | |
| 112 | return 0; |
| 113 | } |
| 114 | |
| 115 | /* |
| 116 | * Iccmax table from Doc #337344 Section 7.2 DC Specifications for CFL. |
| 117 | * Iccmax table from Doc #338023 Section 7.2 DC Specifications for WHL. |
| 118 | * Iccmax table from Doc #606599 Section 7.2 DC Specifications for CML. |
| 119 | * |
| 120 | * Platform Segment SA IA GT (GT/GTx) |
| 121 | * --------------------------------------------------------------------- |
| 122 | * CFL-U (28W) GT3 quad 8.5 64 64 |
| 123 | * CFL-U (28W) GT3 dual 8.5 64 64 |
| 124 | * |
| 125 | * CFL-H (45W) GT2 hex 11.1 128 0 |
| 126 | * CFL-H (45W) GT2 quad 11.1 86 0 |
| 127 | * |
| 128 | * CFL-S (95W) GT2 octa 11.1 193 45 |
| 129 | * |
| 130 | * CFL-S (95W) GT2 hex 11.1 138 45 |
| 131 | * CFL-S (65W) GT2 hex 11.1 133 45 |
| 132 | * CFL-S (80W) GT2 hex 11.1 133 45 |
| 133 | * CFL-S (35W) GT2 hex 11.1 104 35 |
| 134 | * |
| 135 | * CFL-S (91W) GT2 quad 11.1 100 45 |
| 136 | * CFL-S (83W) GT2 quad 11.1 100 45 |
| 137 | * CFL-S (71W) GT2 quad 11.1 100 45 |
| 138 | * CFL-S (65W) GT2 quad 11.1 79 45 |
| 139 | * CFL-S (62W) GT2 quad 11.1 79 45 |
| 140 | * CFL-S (35W) GT2 quad 11.1 66 35 |
| 141 | * |
| 142 | * CFL-S (58W) GT2 dual 11.1 79 45 |
| 143 | * CFL-S (54W) GT2 dual 11.1 58 45 |
| 144 | * CFL-S (35W) GT2 dual 11.1 40 35 |
| 145 | * |
| 146 | * CNL-U (15W) 13 34 0 |
| 147 | * |
| 148 | * WHL-U (15W) GT2 quad 6 70 31 |
| 149 | * WHL-U (15W) GT2 dual 6 35 31 |
| 150 | * |
| 151 | * CML-U v1/v2 (15W) GT2 hex 6 85(70) 31 |
| 152 | * CML-U v1/v2 (15W) GT2 quad 6 85(70) 31 |
| 153 | * CML-U v1/v2 (15W) GT2 dual 6 35 31 |
| 154 | * |
| 155 | * CML-H (65W) GT2 octa 11.1 192(165) 32 |
| 156 | * CML-H (45W) GT2 octa 11.1 165(140) 32 |
| 157 | * CML-H (45W) GT2 hex 11.1 140(128) 32 |
| 158 | * CML-H (45W) GT2 quad 11.1 105(86) 32 |
| 159 | * |
| 160 | * CML-S (125W)GT2 deca 11.1 245(210) 35 |
| 161 | * CML-S (125W)GT2 octa 11.1 245(210) 35 |
| 162 | * CML-S (125W)GT2 hex 11.1 140 35 |
| 163 | * CML-S XeonW (80W) GT2 deca 11.1 210 35 |
| 164 | * CML-S XeonW (80W) GT2 octa 11.1 210 35 |
| 165 | * CML-S XeonW (80W) GT2 hex 11.1 140 35 |
| 166 | * CML-S (65W) GT2 deca 11.1 210(175) 35 |
| 167 | * CML-S (65W) GT2 octa 11.1 210(175) 35 |
| 168 | * CML-S (65W) GT2 hex 11.1 140 35 |
| 169 | * CML-S (35W) GT2 deca 11.1 140(104) 35 |
| 170 | * CML-S (35W) GT2 octa 11.1 140(104) 35 |
| 171 | * CML-S (35W) GT2 hex 11.1 104 35 |
| 172 | * |
| 173 | * GT0 versions are the same as GT2/GT3, but have GT/GTx set to 0. |
| 174 | * The above values in () are for baseline. |
| 175 | */ |
| 176 | |
| 177 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CNL_ID_U) { |
| 178 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(13, 34, 0, 0) }, |
| 179 | }; |
| 180 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CNL_ID_Y) { |
| 181 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(13, 34, 0, 0) }, |
| 182 | }; |
| 183 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_WHL_ID_W_4) { |
| 184 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(6, 70, 31, 31) }, |
| 185 | }; |
| 186 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_WHL_ID_W_2) { |
| 187 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(6, 35, 31, 31) }, |
| 188 | }; |
| 189 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_U) { |
| 190 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(8.5, 64, 64, 64) }, |
| 191 | }; |
| 192 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_U_2) { |
| 193 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(8.5, 64, 64, 64) }, |
| 194 | }; |
| 195 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H_8) { /* undocumented */ |
| 196 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 128, 0, 0) }, |
| 197 | }; |
| 198 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H) { |
| 199 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 128, 0, 0) }, |
| 200 | }; |
| 201 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H_4) { |
| 202 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 86, 0, 0) }, |
| 203 | }; |
| 204 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2) { |
| 205 | { 58, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 79, 35, 35) }, |
| 206 | { 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 58, 45, 45) }, |
| 207 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 40, 35, 35) }, |
| 208 | }; |
| 209 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8) { |
| 210 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) }, |
| 211 | }; |
| 212 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8) { |
| 213 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) }, |
| 214 | }; |
| 215 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S) { |
| 216 | { 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 138, 45, 45) }, |
| 217 | { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 133, 45, 45) }, |
| 218 | { 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 45, 45) }, |
| 219 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) }, |
| 220 | }; |
| 221 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6) { |
| 222 | { 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 138, 45, 45) }, |
| 223 | { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 133, 45, 45) }, |
| 224 | { 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 45, 45) }, |
| 225 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) }, |
| 226 | }; |
| 227 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6) { |
| 228 | { 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 138, 45, 45) }, |
| 229 | { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 133, 45, 45) }, |
| 230 | { 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 45, 45) }, |
| 231 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) }, |
| 232 | }; |
| 233 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4) { |
| 234 | { 71, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 100, 45, 45) }, |
| 235 | { 62, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 79, 45, 45) }, |
| 236 | { 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 45, 45) }, |
| 237 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 35, 35) }, |
| 238 | }; |
| 239 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_ULT) { |
| 240 | { 0, performance, VR_CFG_ALL_DOMAINS_ICC(6, 85, 31, 31) }, |
| 241 | { 0, baseline, VR_CFG_ALL_DOMAINS_ICC(6, 70, 31, 31) }, |
| 242 | }; |
| 243 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_ULT_6_2) { |
| 244 | { 0, performance, VR_CFG_ALL_DOMAINS_ICC(6, 85, 31, 31) }, |
| 245 | { 0, baseline, VR_CFG_ALL_DOMAINS_ICC(6, 70, 31, 31) }, |
| 246 | }; |
| 247 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_ULT_2_2) { |
| 248 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(6, 35, 31, 31) }, |
| 249 | }; |
| 250 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_H_8_2) { |
| 251 | { 65, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 165, 32, 32) }, |
| 252 | { 65, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 192, 32, 32) }, |
| 253 | { 0, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32) }, |
| 254 | { 0, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 165, 32, 32) }, |
| 255 | }; |
| 256 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_H) { |
| 257 | { 0, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32) }, |
| 258 | { 0, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32) }, |
| 259 | }; |
| 260 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_H_4_2) { |
| 261 | { 0, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 105, 32, 32) }, |
| 262 | { 0, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 86, 32, 32) }, |
| 263 | }; |
| 264 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2) { |
| 265 | {125, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 245, 35, 35) }, |
| 266 | {125, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) }, |
| 267 | { 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) }, |
| 268 | { 65, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) }, |
| 269 | { 65, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 175, 35, 35) }, |
| 270 | { 0, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35) }, |
| 271 | { 0, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) }, |
| 272 | }; |
| 273 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2) { |
| 274 | {125, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 245, 35, 35) }, |
| 275 | {125, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) }, |
| 276 | { 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) }, |
| 277 | { 65, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) }, |
| 278 | { 65, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 175, 35, 35) }, |
| 279 | { 0, performance, VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35) }, |
| 280 | { 0, baseline, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) }, |
| 281 | }; |
| 282 | VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2) { |
| 283 | { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35) }, |
| 284 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) }, |
| 285 | }; |
| 286 | |
| 287 | static const struct vr_lookup vr_config_icc[] = { |
| 288 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CNL_ID_U), |
| 289 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CNL_ID_Y), |
| 290 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_WHL_ID_W_4), |
| 291 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_WHL_ID_W_2), |
| 292 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_U), |
| 293 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_U_2), |
| 294 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H_8), |
| 295 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H), |
| 296 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H_4), |
| 297 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2), |
| 298 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8), |
| 299 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8), |
| 300 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S), |
| 301 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6), |
| 302 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6), |
| 303 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4), |
| 304 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_ULT), |
| 305 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_ULT_6_2), |
| 306 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_ULT_2_2), |
| 307 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_H_8_2), |
| 308 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_H), |
| 309 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_H_4_2), |
| 310 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2), |
| 311 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2), |
| 312 | VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2), |
| 313 | }; |
| 314 | |
| 315 | |
| 316 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CNL_ID_U) { |
| 317 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) }, |
| 318 | }; |
| 319 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CNL_ID_Y) { |
| 320 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) }, |
| 321 | }; |
| 322 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_WHL_ID_W_4) { /* unspecified */ |
| 323 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 0, 0) }, |
| 324 | }; |
| 325 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_WHL_ID_W_2) { /* unspecified */ |
| 326 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 0, 0) }, |
| 327 | }; |
| 328 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_U) { |
| 329 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) }, |
| 330 | }; |
| 331 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_U_2) { |
| 332 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) }, |
| 333 | }; |
| 334 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H_8) { |
| 335 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 2.7, 2.7) }, |
| 336 | }; |
| 337 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H) { |
| 338 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 2.7, 2.7) }, |
| 339 | }; |
| 340 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H_4) { |
| 341 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 2.7, 2.7) }, |
| 342 | }; |
| 343 | /* FIXME: Loadline isn't specified for S-series, using H-series default */ |
| 344 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4) { |
| 345 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) }, |
| 346 | }; |
| 347 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4) { |
| 348 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) }, |
| 349 | }; |
| 350 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2) { |
| 351 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) }, |
| 352 | }; |
| 353 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8) { |
| 354 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.6, 3.1, 3.1) }, |
| 355 | }; |
| 356 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8) { |
| 357 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.6, 3.1, 3.1) }, |
| 358 | }; |
| 359 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S) { |
| 360 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) }, |
| 361 | }; |
| 362 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6) { |
| 363 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) }, |
| 364 | }; |
| 365 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6) { |
| 366 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) }, |
| 367 | }; |
| 368 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4) { |
| 369 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) }, |
| 370 | }; |
| 371 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_ULT) { |
| 372 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 3.1, 3.1) }, |
| 373 | }; |
| 374 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_ULT_6_2) { |
| 375 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 3.1, 3.1) }, |
| 376 | }; |
| 377 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_ULT_2_2) { |
| 378 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 3.1, 3.1) }, |
| 379 | }; |
| 380 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_H_8_2) { |
| 381 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7) }, |
| 382 | }; |
| 383 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_H) { |
| 384 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7) }, |
| 385 | }; |
| 386 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_H_4_2) { |
| 387 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7) }, |
| 388 | }; |
| 389 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2) { |
| 390 | { 36, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0) }, |
| 391 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) }, |
| 392 | }; |
| 393 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2) { |
| 394 | { 36, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0) }, |
| 395 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) }, |
| 396 | }; |
| 397 | VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2) { |
| 398 | {125, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0) }, |
| 399 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) }, |
| 400 | }; |
| 401 | |
| 402 | static const struct vr_lookup vr_config_ll[] = { |
| 403 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CNL_ID_U), |
| 404 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CNL_ID_Y), |
| 405 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_WHL_ID_W_4), |
| 406 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_WHL_ID_W_2), |
| 407 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_U), |
| 408 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_U_2), |
| 409 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H_8), |
| 410 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H), |
| 411 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H_4), |
| 412 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4), |
| 413 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4), |
| 414 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2), |
| 415 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8), |
| 416 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8), |
| 417 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S), |
| 418 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6), |
| 419 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6), |
| 420 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4), |
| 421 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_ULT), |
| 422 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_ULT_6_2), |
| 423 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_ULT_2_2), |
| 424 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_H_8_2), |
| 425 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_H), |
| 426 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_H_4_2), |
| 427 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2), |
| 428 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2), |
| 429 | VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2), |
| 430 | }; |
| 431 | |
| 432 | |
| 433 | VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_ULT) { |
| 434 | { 0, baseline, VR_CFG_ALL_DOMAINS_TDC(4, 48, 22, 22) }, |
| 435 | { 0, performance, VR_CFG_ALL_DOMAINS_TDC(4, 58, 22, 22) }, |
| 436 | }; |
| 437 | VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_ULT_6_2) { |
| 438 | { 0, baseline, VR_CFG_ALL_DOMAINS_TDC(4, 48, 22, 22) }, |
| 439 | { 0, performance, VR_CFG_ALL_DOMAINS_TDC(4, 58, 22, 22) }, |
| 440 | }; |
| 441 | VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_ULT_2_2) { |
| 442 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(4, 24, 22, 22) }, |
| 443 | }; |
| 444 | VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_H_8_2) { |
| 445 | { 65, performance, VR_CFG_ALL_DOMAINS_TDC(10, 146, 25, 25) }, |
| 446 | { 65, baseline, VR_CFG_ALL_DOMAINS_TDC(10, 117, 25, 25) }, |
| 447 | { 0, performance, VR_CFG_ALL_DOMAINS_TDC(10, 125, 25, 25) }, |
| 448 | { 0, baseline, VR_CFG_ALL_DOMAINS_TDC(10, 86, 25, 25) }, |
| 449 | }; |
| 450 | |
| 451 | VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_H) { |
| 452 | { 0, performance, VR_CFG_ALL_DOMAINS_TDC(10, 92, 25, 25) }, |
| 453 | { 0, baseline, VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25) }, |
| 454 | }; |
| 455 | VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_H_4_2) { |
| 456 | { 0, performance, VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25) }, |
| 457 | { 0, baseline, VR_CFG_ALL_DOMAINS_TDC(10, 60, 25, 25) }, |
| 458 | }; |
| 459 | VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2) { |
| 460 | { 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 175, 28, 28) }, |
| 461 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 28, 28) }, |
| 462 | }; |
| 463 | VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2) { |
| 464 | { 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 175, 28, 28) }, |
| 465 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 28, 28) }, |
| 466 | }; |
| 467 | VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2) { |
| 468 | {125, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 132, 28, 28) }, |
| 469 | { 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 104, 28, 28) }, |
| 470 | { 0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 28, 28) }, |
| 471 | }; |
| 472 | |
| 473 | static const struct vr_lookup vr_config_tdc[] = { |
| 474 | VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_ULT), |
| 475 | VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_ULT_6_2), |
| 476 | VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_ULT_2_2), |
| 477 | VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_H_8_2), |
| 478 | VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_H), |
| 479 | VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_H_4_2), |
| 480 | VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2), |
| 481 | VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2), |
| 482 | VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2), |
| 483 | }; |
| 484 | |
| 485 | |
| 486 | static uint16_t get_sku_voltagelimit(int domain) |
| 487 | { |
| 488 | return 1520; |
| 489 | } |
| 490 | |
| 491 | static uint16_t get_sku_icc_max(const int domain, |
| 492 | const uint16_t tdp, |
| 493 | const uint16_t mch_id, |
| 494 | const uint16_t igd_id) |
| 495 | { |
| 496 | if (igd_id == 0xffff && ((domain == VR_GT_SLICED) || (domain == VR_GT_UNSLICED))) |
| 497 | return 0; |
| 498 | |
| 499 | return load_table(vr_config_icc, ARRAY_SIZE(vr_config_icc), domain, tdp, mch_id); |
| 500 | } |
| 501 | |
| 502 | void fill_vr_domain_config(void *params, |
| 503 | int domain, const struct vr_config *chip_cfg) |
| 504 | { |
| 505 | FSP_S_CONFIG *vr_params = (FSP_S_CONFIG *)params; |
| 506 | const struct vr_config *cfg; |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 507 | static uint16_t mch_id = 0, igd_id = 0; |
Patrick Rudolph | 9de8c80 | 2020-05-18 12:03:52 +0200 | [diff] [blame^] | 508 | const uint16_t tdp = cpu_get_power_max(); |
| 509 | |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 510 | if (!mch_id) { |
| 511 | struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 512 | mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; |
| 513 | } |
| 514 | if (!igd_id) { |
| 515 | struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); |
| 516 | igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; |
| 517 | } |
| 518 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 519 | if (domain < 0 || domain >= NUM_VR_DOMAINS) |
| 520 | return; |
| 521 | |
| 522 | /* Use device tree override if requested. */ |
| 523 | if (chip_cfg->vr_config_enable) |
| 524 | cfg = chip_cfg; |
| 525 | else |
| 526 | cfg = &default_configs[domain]; |
| 527 | |
| 528 | vr_params->VrConfigEnable[domain] = cfg->vr_config_enable; |
| 529 | vr_params->Psi1Threshold[domain] = cfg->psi1threshold; |
| 530 | vr_params->Psi2Threshold[domain] = cfg->psi2threshold; |
| 531 | vr_params->Psi3Threshold[domain] = cfg->psi3threshold; |
| 532 | vr_params->Psi3Enable[domain] = cfg->psi3enable; |
| 533 | vr_params->Psi4Enable[domain] = cfg->psi4enable; |
| 534 | vr_params->ImonSlope[domain] = cfg->imon_slope; |
| 535 | vr_params->ImonOffset[domain] = cfg->imon_offset; |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 536 | |
| 537 | /* If board provided non-zero value, use it. */ |
| 538 | if (cfg->voltage_limit) |
| 539 | vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; |
| 540 | else |
| 541 | vr_params->VrVoltageLimit[domain] = get_sku_voltagelimit(domain); |
| 542 | |
| 543 | if (cfg->icc_max) |
| 544 | vr_params->IccMax[domain] = cfg->icc_max; |
| 545 | else |
Patrick Rudolph | 9de8c80 | 2020-05-18 12:03:52 +0200 | [diff] [blame^] | 546 | vr_params->IccMax[domain] = get_sku_icc_max(domain, tdp, mch_id, igd_id); |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 547 | |
| 548 | if (cfg->ac_loadline) |
| 549 | vr_params->AcLoadline[domain] = cfg->ac_loadline; |
| 550 | else |
Patrick Rudolph | 9de8c80 | 2020-05-18 12:03:52 +0200 | [diff] [blame^] | 551 | vr_params->AcLoadline[domain] = load_table(vr_config_ll, |
| 552 | ARRAY_SIZE(vr_config_ll), |
| 553 | domain, tdp, mch_id); |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 554 | |
| 555 | if (cfg->dc_loadline) |
| 556 | vr_params->DcLoadline[domain] = cfg->dc_loadline; |
| 557 | else |
Patrick Rudolph | 9de8c80 | 2020-05-18 12:03:52 +0200 | [diff] [blame^] | 558 | vr_params->DcLoadline[domain] = load_table(vr_config_ll, |
| 559 | ARRAY_SIZE(vr_config_ll), |
| 560 | domain, tdp, mch_id); |
Marx Wang | 9318d6d | 2020-02-07 16:44:14 +0800 | [diff] [blame] | 561 | |
| 562 | vr_params->TdcEnable[domain] = !cfg->tdc_disable; |
| 563 | |
| 564 | if (cfg->tdc_powerlimit) |
| 565 | vr_params->TdcPowerLimit[domain] = cfg->tdc_powerlimit; |
| 566 | else |
Patrick Rudolph | 9de8c80 | 2020-05-18 12:03:52 +0200 | [diff] [blame^] | 567 | vr_params->TdcPowerLimit[domain] = load_table(vr_config_tdc, |
| 568 | ARRAY_SIZE(vr_config_tdc), |
| 569 | domain, tdp, mch_id); |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 570 | } |