Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | */ |
| 16 | |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 17 | #include <device/pci_ids.h> |
| 18 | #include <device/pci_ops.h> |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 19 | #include <fsp/api.h> |
| 20 | #include <soc/ramstage.h> |
| 21 | #include <soc/vr_config.h> |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 22 | #include <console/console.h> |
| 23 | #include <intelblocks/cpulib.h> |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 24 | |
| 25 | static const struct vr_config default_configs[NUM_VR_DOMAINS] = { |
Roy Mingi Park | 1ac2ad0 | 2019-02-13 11:10:45 -0800 | [diff] [blame] | 26 | [VR_SYSTEM_AGENT] = { |
| 27 | .vr_config_enable = 1, |
| 28 | .psi1threshold = VR_CFG_AMP(20), |
| 29 | .psi2threshold = VR_CFG_AMP(5), |
| 30 | .psi3threshold = VR_CFG_AMP(1), |
| 31 | .psi3enable = 1, |
| 32 | .psi4enable = 1, |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 33 | .imon_slope = 0, |
| 34 | .imon_offset = 0, |
| 35 | .icc_max = 0, |
Roy Mingi Park | 1ac2ad0 | 2019-02-13 11:10:45 -0800 | [diff] [blame] | 36 | .voltage_limit = 1520, |
| 37 | }, |
| 38 | [VR_IA_CORE] = { |
| 39 | .vr_config_enable = 1, |
| 40 | .psi1threshold = VR_CFG_AMP(20), |
| 41 | .psi2threshold = VR_CFG_AMP(5), |
| 42 | .psi3threshold = VR_CFG_AMP(1), |
| 43 | .psi3enable = 1, |
| 44 | .psi4enable = 1, |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 45 | .imon_slope = 0, |
| 46 | .imon_offset = 0, |
| 47 | .icc_max = 0, |
Roy Mingi Park | 1ac2ad0 | 2019-02-13 11:10:45 -0800 | [diff] [blame] | 48 | .voltage_limit = 1520, |
| 49 | }, |
| 50 | [VR_GT_UNSLICED] = { |
| 51 | .vr_config_enable = 1, |
| 52 | .psi1threshold = VR_CFG_AMP(20), |
| 53 | .psi2threshold = VR_CFG_AMP(5), |
| 54 | .psi3threshold = VR_CFG_AMP(1), |
| 55 | .psi3enable = 1, |
| 56 | .psi4enable = 1, |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 57 | .imon_slope = 0, |
| 58 | .imon_offset = 0, |
| 59 | .icc_max = 0, |
Roy Mingi Park | 1ac2ad0 | 2019-02-13 11:10:45 -0800 | [diff] [blame] | 60 | .voltage_limit = 1520, |
| 61 | }, |
| 62 | [VR_GT_SLICED] = { |
| 63 | .vr_config_enable = 1, |
| 64 | .psi1threshold = VR_CFG_AMP(20), |
| 65 | .psi2threshold = VR_CFG_AMP(5), |
| 66 | .psi3threshold = VR_CFG_AMP(1), |
| 67 | .psi3enable = 1, |
| 68 | .psi4enable = 1, |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 69 | .imon_slope = 0, |
| 70 | .imon_offset = 0, |
| 71 | .icc_max = 0, |
Roy Mingi Park | 1ac2ad0 | 2019-02-13 11:10:45 -0800 | [diff] [blame] | 72 | .voltage_limit = 1520, |
| 73 | }, |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 74 | }; |
| 75 | |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 76 | |
| 77 | static uint16_t get_sku_icc_max(int domain) |
| 78 | { |
| 79 | const uint16_t tdp = cpu_get_power_max(); |
Jamie Chen | 3ccae2b | 2019-12-20 17:28:38 +0800 | [diff] [blame] | 80 | config_t *cfg = config_of_soc(); |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 81 | |
| 82 | static uint16_t mch_id = 0, igd_id = 0; |
| 83 | if (!mch_id) { |
| 84 | struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 85 | mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; |
| 86 | } |
| 87 | if (!igd_id) { |
| 88 | struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); |
| 89 | igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; |
| 90 | } |
| 91 | |
| 92 | /* |
| 93 | * Iccmax table from Doc #337344 Section 7.2 DC Specifications for CFL. |
| 94 | * Iccmax table from Doc #338023 Section 7.2 DC Specifications for WHL. |
Jamie Chen | 3ccae2b | 2019-12-20 17:28:38 +0800 | [diff] [blame] | 95 | * Iccmax table from Doc #606599 Section 7.2 DC Specifications for CML. |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 96 | * |
| 97 | * Platform Segment SA IA GT (GT/GTx) |
| 98 | * --------------------------------------------------------------------- |
| 99 | * CFL-U (28W) GT3 quad 8.5 64 64 |
| 100 | * CFL-U (28W) GT3 dual 8.5 64 64 |
| 101 | * |
| 102 | * CFL-H (45W) GT2 hex 11.1 128 0 |
| 103 | * CFL-H (45W) GT2 quad 11.1 86 0 |
| 104 | * |
| 105 | * CFL-S (95W) GT2 octa 11.1 193 45 |
| 106 | * |
| 107 | * CFL-S (95W) GT2 hex 11.1 138 45 |
| 108 | * CFL-S (65W) GT2 hex 11.1 133 45 |
| 109 | * CFL-S (80W) GT2 hex 11.1 133 45 |
| 110 | * CFL-S (35W) GT2 hex 11.1 104 35 |
| 111 | * |
| 112 | * CFL-S (91W) GT2 quad 11.1 100 45 |
| 113 | * CFL-S (83W) GT2 quad 11.1 100 45 |
| 114 | * CFL-S (71W) GT2 quad 11.1 100 45 |
| 115 | * CFL-S (65W) GT2 quad 11.1 79 45 |
| 116 | * CFL-S (62W) GT2 quad 11.1 79 45 |
| 117 | * CFL-S (35W) GT2 quad 11.1 66 35 |
| 118 | * |
| 119 | * CFL-S (58W) GT2 dual 11.1 79 45 |
| 120 | * CFL-S (54W) GT2 dual 11.1 58 45 |
| 121 | * CFL-S (35W) GT2 dual 11.1 40 35 |
| 122 | * |
| 123 | * CNL-U (15W) 13 34 0 |
| 124 | * |
| 125 | * WHL-U (15W) GT2 quad 6 70 31 |
| 126 | * WHL-U (15W) GT2 dual 6 35 31 |
| 127 | * |
Jamie Chen | 3ccae2b | 2019-12-20 17:28:38 +0800 | [diff] [blame] | 128 | * CML-U v1/v2 (15W) GT2 hex 6 85(70) 31 |
| 129 | * CML-U v1/v2 (15W) GT2 quad 6 85(70) 31 |
| 130 | * CML-U v1/v2 (15W) GT2 dual 6 35 31 |
| 131 | * |
| 132 | * CML-H (65W) GT2 octa 11.1 192(165) 32 |
| 133 | * CML-H (45W) GT2 octa 11.1 165(140) 32 |
| 134 | * CML-H (45W) GT2 hex 11.1 140(128) 32 |
| 135 | * CML-H (45W) GT2 quad 11.1 105(86) 32 |
| 136 | * |
| 137 | * CML-S (125W)GT2 deca 11.1 245(210) 35 |
| 138 | * CML-S (125W)GT2 octa 11.1 245(210) 35 |
| 139 | * CML-S (125W)GT2 hex 11.1 140 35 |
| 140 | * CML-S XeonW (80W) GT2 deca 11.1 210 35 |
| 141 | * CML-S XeonW (80W) GT2 octa 11.1 210 35 |
| 142 | * CML-S XeonW (80W) GT2 hex 11.1 140 35 |
| 143 | * CML-S (65W) GT2 deca 11.1 210(175) 35 |
| 144 | * CML-S (65W) GT2 octa 11.1 210(175) 35 |
| 145 | * CML-S (65W) GT2 hex 11.1 140 35 |
| 146 | * CML-S (35W) GT2 deca 11.1 140(104) 35 |
| 147 | * CML-S (35W) GT2 octa 11.1 140(104) 35 |
| 148 | * CML-S (35W) GT2 hex 11.1 104 35 |
| 149 | * |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 150 | * GT0 versions are the same as GT2/GT3, but have GT/GTx set to 0. |
Jamie Chen | 3ccae2b | 2019-12-20 17:28:38 +0800 | [diff] [blame] | 151 | * The above values in () are for baseline. |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 152 | */ |
| 153 | |
| 154 | if (igd_id == 0xffff && ((domain == VR_GT_SLICED) || (domain == VR_GT_UNSLICED))) |
| 155 | return 0; |
| 156 | |
| 157 | switch (mch_id) { |
| 158 | case PCI_DEVICE_ID_INTEL_CNL_ID_U: /* fallthrough */ |
| 159 | case PCI_DEVICE_ID_INTEL_CNL_ID_Y: { |
| 160 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(13, 34, 0, 0); |
| 161 | |
| 162 | return icc_max[domain]; |
| 163 | } |
| 164 | case PCI_DEVICE_ID_INTEL_WHL_ID_W_4: { |
| 165 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6, 70, 31, 31); |
| 166 | |
| 167 | return icc_max[domain]; |
| 168 | } |
| 169 | case PCI_DEVICE_ID_INTEL_WHL_ID_W_2: { |
| 170 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6, 35, 31, 31); |
| 171 | |
| 172 | return icc_max[domain]; |
| 173 | } |
| 174 | case PCI_DEVICE_ID_INTEL_CFL_ID_U: /* fallthrough */ |
| 175 | case PCI_DEVICE_ID_INTEL_CFL_ID_U_2: { |
| 176 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(8.5, 64, 64, 64); |
| 177 | |
| 178 | return icc_max[domain]; |
| 179 | } |
| 180 | case PCI_DEVICE_ID_INTEL_CFL_ID_H_8: /* fallthrough - undocumented */ |
| 181 | case PCI_DEVICE_ID_INTEL_CFL_ID_H: { /* 6 core */ |
| 182 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 128, 0, 0); |
| 183 | |
| 184 | return icc_max[domain]; |
| 185 | } |
| 186 | case PCI_DEVICE_ID_INTEL_CFL_ID_H_4: { /* 4 core */ |
| 187 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 86, 0, 0); |
| 188 | |
| 189 | return icc_max[domain]; |
| 190 | } |
| 191 | case PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2: { /* 2 core */ |
| 192 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 40, 35, 35); |
| 193 | |
| 194 | if (tdp >= 54) { |
| 195 | if (tdp >= 58) |
| 196 | icc_max[VR_IA_CORE] = VR_CFG_AMP(79); |
| 197 | else |
| 198 | icc_max[VR_IA_CORE] = VR_CFG_AMP(58); |
| 199 | |
| 200 | icc_max[VR_GT_SLICED] = VR_CFG_AMP(45); |
| 201 | icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(45); |
| 202 | } |
| 203 | |
| 204 | return icc_max[domain]; |
| 205 | } |
| 206 | case PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8: { |
| 207 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45); |
| 208 | |
| 209 | return icc_max[domain]; |
| 210 | } |
| 211 | case PCI_DEVICE_ID_INTEL_CFL_ID_S: /* fallthrough */ |
| 212 | case PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6: /* fallthrough */ |
| 213 | case PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6: { |
| 214 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35); |
| 215 | if (tdp >= 54) { |
| 216 | if (tdp >= 95) |
| 217 | icc_max[VR_IA_CORE] = VR_CFG_AMP(138); |
| 218 | else if (tdp >= 65) |
| 219 | icc_max[VR_IA_CORE] = VR_CFG_AMP(133); |
| 220 | |
| 221 | icc_max[VR_GT_SLICED] = VR_CFG_AMP(45); |
| 222 | icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(45); |
| 223 | } |
| 224 | |
| 225 | return icc_max[domain]; |
| 226 | } |
| 227 | case PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4: /* fallthrough */ |
| 228 | case PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4: /* fallthrough */ |
| 229 | case PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4: { |
| 230 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 35, 35); |
| 231 | if (tdp >= 54) { |
| 232 | if (tdp >= 71) |
| 233 | icc_max[VR_IA_CORE] = VR_CFG_AMP(100); |
| 234 | else if (tdp >= 62) |
| 235 | icc_max[VR_IA_CORE] = VR_CFG_AMP(79); |
| 236 | |
| 237 | icc_max[VR_GT_SLICED] = VR_CFG_AMP(45); |
| 238 | icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(45); |
| 239 | } |
| 240 | |
| 241 | return icc_max[domain]; |
| 242 | } |
Jamie Chen | 3ccae2b | 2019-12-20 17:28:38 +0800 | [diff] [blame] | 243 | case PCI_DEVICE_ID_INTEL_CML_ULT: /* fallthrough */ |
| 244 | case PCI_DEVICE_ID_INTEL_CML_ULT_6_2: { |
| 245 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6, 85, 31, 31); |
| 246 | if (cfg->cpu_pl2_4_cfg == baseline) |
| 247 | icc_max[VR_IA_CORE] = VR_CFG_AMP(70); |
| 248 | |
| 249 | return icc_max[domain]; |
| 250 | } |
| 251 | case PCI_DEVICE_ID_INTEL_CML_ULT_2_2: { |
| 252 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6, 35, 31, 31); |
| 253 | |
| 254 | return icc_max[domain]; |
| 255 | } |
| 256 | case PCI_DEVICE_ID_INTEL_CML_H_8_2: { |
| 257 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 192, 32, 32); |
| 258 | if (tdp >= 65) { /* 65W */ |
| 259 | if (cfg->cpu_pl2_4_cfg == baseline) |
| 260 | icc_max[VR_IA_CORE] = VR_CFG_AMP(165); |
| 261 | else |
| 262 | icc_max[VR_IA_CORE] = VR_CFG_AMP(192); |
| 263 | } else { /* 45W */ |
| 264 | if (cfg->cpu_pl2_4_cfg == baseline) |
| 265 | icc_max[VR_IA_CORE] = VR_CFG_AMP(140); |
| 266 | else |
| 267 | icc_max[VR_IA_CORE] = VR_CFG_AMP(165); |
| 268 | } |
| 269 | return icc_max[domain]; |
| 270 | } |
| 271 | case PCI_DEVICE_ID_INTEL_CML_H: { |
| 272 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32); |
| 273 | |
| 274 | if (cfg->cpu_pl2_4_cfg == baseline) |
| 275 | icc_max[VR_IA_CORE] = VR_CFG_AMP(128); |
| 276 | |
| 277 | return icc_max[domain]; |
| 278 | } |
| 279 | case PCI_DEVICE_ID_INTEL_CML_H_4_2: { |
| 280 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 105, 32, 32); |
| 281 | |
| 282 | if (cfg->cpu_pl2_4_cfg == baseline) |
| 283 | icc_max[VR_IA_CORE] = VR_CFG_AMP(86); |
| 284 | |
| 285 | return icc_max[domain]; |
| 286 | } |
| 287 | case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: /* fallthrough */ |
| 288 | case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: { |
| 289 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35); |
| 290 | if (tdp >= 125) /* 125W */ |
| 291 | if (cfg->cpu_pl2_4_cfg == baseline) |
| 292 | icc_max[VR_IA_CORE] = VR_CFG_AMP(210); |
| 293 | else |
| 294 | icc_max[VR_IA_CORE] = VR_CFG_AMP(245); |
| 295 | else if (tdp >= 80) /* 80W */ |
| 296 | icc_max[VR_IA_CORE] = VR_CFG_AMP(210); |
| 297 | else if (tdp >= 65) /* 65W */ |
| 298 | if (cfg->cpu_pl2_4_cfg == baseline) |
| 299 | icc_max[VR_IA_CORE] = VR_CFG_AMP(175); |
| 300 | else |
| 301 | icc_max[VR_IA_CORE] = VR_CFG_AMP(210); |
| 302 | else /* 35W */ |
| 303 | if (cfg->cpu_pl2_4_cfg == baseline) |
| 304 | icc_max[VR_IA_CORE] = VR_CFG_AMP(104); |
| 305 | else |
| 306 | icc_max[VR_IA_CORE] = VR_CFG_AMP(140); |
| 307 | |
| 308 | return icc_max[domain]; |
| 309 | } |
| 310 | case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: { |
| 311 | uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35); |
| 312 | if (tdp >= 65) /* 125W or 80W or 65W */ |
| 313 | icc_max[VR_IA_CORE] = VR_CFG_AMP(140); |
| 314 | else /* 35W */ |
| 315 | icc_max[VR_IA_CORE] = VR_CFG_AMP(104); |
| 316 | |
| 317 | return icc_max[domain]; |
| 318 | } |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 319 | default: |
| 320 | printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); |
| 321 | } |
| 322 | return 0; |
| 323 | } |
| 324 | |
| 325 | static uint16_t get_sku_ac_dc_loadline(const int domain) |
| 326 | { |
Jamie Chen | 3ccae2b | 2019-12-20 17:28:38 +0800 | [diff] [blame] | 327 | const uint16_t tdp = cpu_get_power_max(); |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 328 | static uint16_t mch_id = 0; |
| 329 | if (!mch_id) { |
| 330 | struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 331 | mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; |
| 332 | } |
| 333 | |
| 334 | switch (mch_id) { |
| 335 | case PCI_DEVICE_ID_INTEL_WHL_ID_W_4: /* fallthrough */ |
| 336 | case PCI_DEVICE_ID_INTEL_CFL_ID_H_8: /* fallthrough */ |
| 337 | case PCI_DEVICE_ID_INTEL_CFL_ID_H: /* fallthrough */ |
| 338 | case PCI_DEVICE_ID_INTEL_CFL_ID_H_4: { /* fallthrough */ |
| 339 | uint16_t loadline[NUM_VR_DOMAINS] = |
| 340 | VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 2.7, 2.7); |
| 341 | if (mch_id == PCI_DEVICE_ID_INTEL_WHL_ID_W_4) { |
| 342 | loadline[VR_GT_SLICED] = 0; /* unspecified */ |
| 343 | loadline[VR_GT_UNSLICED] = 0; /* unspecified */ |
| 344 | } |
| 345 | return loadline[domain]; |
| 346 | } |
| 347 | case PCI_DEVICE_ID_INTEL_WHL_ID_W_2: /* fallthrough */ |
| 348 | case PCI_DEVICE_ID_INTEL_CFL_ID_U: /* fallthrough */ |
| 349 | case PCI_DEVICE_ID_INTEL_CFL_ID_U_2: /* fallthrough */ |
| 350 | case PCI_DEVICE_ID_INTEL_CNL_ID_U: /* fallthrough */ |
| 351 | case PCI_DEVICE_ID_INTEL_CNL_ID_Y: { |
| 352 | uint16_t loadline[NUM_VR_DOMAINS] = |
| 353 | VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0); |
| 354 | if (mch_id == PCI_DEVICE_ID_INTEL_WHL_ID_W_2) { |
| 355 | loadline[VR_GT_SLICED] = 0; /* unspecified */ |
| 356 | loadline[VR_GT_UNSLICED] = 0; /* unspecified */ |
| 357 | } |
| 358 | return loadline[domain]; |
| 359 | } |
| 360 | case PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8: { |
| 361 | /* FIXME: Loadline isn't specified for S-series, using H-series default */ |
| 362 | const uint16_t loadline[NUM_VR_DOMAINS] = |
| 363 | VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.6, 3.1, 3.1); |
| 364 | return loadline[domain]; |
| 365 | } |
| 366 | case PCI_DEVICE_ID_INTEL_CFL_ID_S: /* fallthrough */ |
| 367 | case PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6: /* fallthrough */ |
| 368 | case PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6: /* fallthrough */ |
| 369 | case PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4: /* fallthrough */ |
| 370 | case PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4: /* fallthrough */ |
| 371 | case PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4: /* fallthrough */ |
| 372 | case PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2: { |
| 373 | /* FIXME: Loadline isn't specified for S-series, using H-series default */ |
| 374 | const uint16_t loadline[NUM_VR_DOMAINS] = |
| 375 | VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1); |
| 376 | return loadline[domain]; |
| 377 | } |
Jamie Chen | 3ccae2b | 2019-12-20 17:28:38 +0800 | [diff] [blame] | 378 | case PCI_DEVICE_ID_INTEL_CML_ULT_2_2: { |
| 379 | const uint16_t loadline[NUM_VR_DOMAINS] = |
| 380 | VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 3.1, 3.1); |
| 381 | return loadline[domain]; |
| 382 | } |
| 383 | case PCI_DEVICE_ID_INTEL_CML_ULT: /* fallthrough */ |
| 384 | case PCI_DEVICE_ID_INTEL_CML_ULT_6_2: { |
| 385 | const uint16_t loadline[NUM_VR_DOMAINS] = |
| 386 | VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 3.1, 3.1); |
| 387 | return loadline[domain]; |
| 388 | } |
| 389 | case PCI_DEVICE_ID_INTEL_CML_H_4_2: /* fallthrough */ |
| 390 | case PCI_DEVICE_ID_INTEL_CML_H: /* fallthrough */ |
| 391 | case PCI_DEVICE_ID_INTEL_CML_H_8_2: { |
| 392 | const uint16_t loadline[NUM_VR_DOMAINS] = |
| 393 | VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7); |
| 394 | return loadline[domain]; |
| 395 | } |
| 396 | case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: { |
| 397 | uint16_t loadline[NUM_VR_DOMAINS] = |
| 398 | VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0); |
| 399 | if (tdp >= 125) |
| 400 | loadline[VR_IA_CORE] = VR_CFG_MOHMS(1.1); |
| 401 | return loadline[domain]; |
| 402 | } |
| 403 | case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: /* fallthrough */ |
| 404 | case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: { |
| 405 | uint16_t loadline[NUM_VR_DOMAINS] = |
| 406 | VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0); |
| 407 | if (tdp > 35) |
| 408 | loadline[VR_IA_CORE] = VR_CFG_MOHMS(1.1); |
| 409 | return loadline[domain]; |
| 410 | } |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 411 | default: |
| 412 | printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); |
| 413 | } |
| 414 | return 0; |
| 415 | } |
| 416 | |
| 417 | static uint16_t get_sku_voltagelimit(int domain) |
| 418 | { |
| 419 | return 1520; |
| 420 | } |
| 421 | |
Marx Wang | 9318d6d | 2020-02-07 16:44:14 +0800 | [diff] [blame^] | 422 | static uint16_t get_sku_tdc_powerlimit(int domain) |
| 423 | { |
| 424 | const uint16_t tdp = cpu_get_power_max(); |
| 425 | const config_t *cfg = config_of_soc(); |
| 426 | |
| 427 | static uint16_t mch_id = 0; |
| 428 | if (!mch_id) { |
| 429 | struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 430 | mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; |
| 431 | } |
| 432 | |
| 433 | switch (mch_id) { |
| 434 | case PCI_DEVICE_ID_INTEL_CML_ULT: |
| 435 | case PCI_DEVICE_ID_INTEL_CML_ULT_6_2: { |
| 436 | uint16_t tdc[NUM_VR_DOMAINS] = |
| 437 | VR_CFG_ALL_DOMAINS_TDC(4, 58, 22, 22); |
| 438 | |
| 439 | if (cfg->cpu_pl2_4_cfg == baseline) |
| 440 | tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(48); |
| 441 | |
| 442 | return tdc[domain]; |
| 443 | } |
| 444 | case PCI_DEVICE_ID_INTEL_CML_ULT_2_2: { |
| 445 | const uint16_t tdc[NUM_VR_DOMAINS] = |
| 446 | VR_CFG_ALL_DOMAINS_TDC(4, 24, 22, 22); |
| 447 | return tdc[domain]; |
| 448 | } |
| 449 | case PCI_DEVICE_ID_INTEL_CML_H_4_2: { |
| 450 | uint16_t tdc[NUM_VR_DOMAINS] = |
| 451 | VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25); |
| 452 | |
| 453 | if (cfg->cpu_pl2_4_cfg == baseline) |
| 454 | tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(60); |
| 455 | |
| 456 | return tdc[domain]; |
| 457 | } |
| 458 | case PCI_DEVICE_ID_INTEL_CML_H: { |
| 459 | uint16_t tdc[NUM_VR_DOMAINS] = |
| 460 | VR_CFG_ALL_DOMAINS_TDC(10, 92, 25, 25); |
| 461 | |
| 462 | if (cfg->cpu_pl2_4_cfg == baseline) |
| 463 | tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(80); |
| 464 | |
| 465 | return tdc[domain]; |
| 466 | } |
| 467 | case PCI_DEVICE_ID_INTEL_CML_H_8_2: { |
| 468 | uint16_t tdc[NUM_VR_DOMAINS] = |
| 469 | VR_CFG_ALL_DOMAINS_TDC(10, 125, 25, 25); |
| 470 | |
| 471 | if (tdp >= 65) /* 65W */ |
| 472 | tdc[VR_IA_CORE] = (cfg->cpu_pl2_4_cfg == baseline) ? |
| 473 | VR_CFG_TDC_AMP(117) : |
| 474 | VR_CFG_TDC_AMP(146); |
| 475 | else /* 45W */ |
| 476 | tdc[VR_IA_CORE] = (cfg->cpu_pl2_4_cfg == baseline) ? |
| 477 | VR_CFG_TDC_AMP(86) : |
| 478 | VR_CFG_TDC_AMP(125); |
| 479 | |
| 480 | return tdc[domain]; |
| 481 | } |
| 482 | case PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2: { |
| 483 | uint16_t tdc[NUM_VR_DOMAINS] = |
| 484 | VR_CFG_ALL_DOMAINS_TDC(10, 74, 28, 28); |
| 485 | |
| 486 | if (tdp >= 125) /* 125W */ |
| 487 | tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(132); |
| 488 | else if (tdp >= 65) /* 80W or 65W */ |
| 489 | tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(104); |
| 490 | else /* 35W */ |
| 491 | tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(74); |
| 492 | |
| 493 | return tdc[domain]; |
| 494 | } |
| 495 | case PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2: |
| 496 | case PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2: { |
| 497 | uint16_t tdc[NUM_VR_DOMAINS] = |
| 498 | VR_CFG_ALL_DOMAINS_TDC(10, 100, 28, 28); |
| 499 | |
| 500 | if (tdp > 35) /* 125W or 80W or 65W */ |
| 501 | tdc[VR_IA_CORE] = VR_CFG_TDC_AMP(175); |
| 502 | |
| 503 | return tdc[domain]; |
| 504 | } |
| 505 | default: |
| 506 | printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in VR-config\n", mch_id); |
| 507 | } |
| 508 | |
| 509 | return 0; |
| 510 | } |
| 511 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 512 | void fill_vr_domain_config(void *params, |
| 513 | int domain, const struct vr_config *chip_cfg) |
| 514 | { |
| 515 | FSP_S_CONFIG *vr_params = (FSP_S_CONFIG *)params; |
| 516 | const struct vr_config *cfg; |
| 517 | |
| 518 | if (domain < 0 || domain >= NUM_VR_DOMAINS) |
| 519 | return; |
| 520 | |
| 521 | /* Use device tree override if requested. */ |
| 522 | if (chip_cfg->vr_config_enable) |
| 523 | cfg = chip_cfg; |
| 524 | else |
| 525 | cfg = &default_configs[domain]; |
| 526 | |
| 527 | vr_params->VrConfigEnable[domain] = cfg->vr_config_enable; |
| 528 | vr_params->Psi1Threshold[domain] = cfg->psi1threshold; |
| 529 | vr_params->Psi2Threshold[domain] = cfg->psi2threshold; |
| 530 | vr_params->Psi3Threshold[domain] = cfg->psi3threshold; |
| 531 | vr_params->Psi3Enable[domain] = cfg->psi3enable; |
| 532 | vr_params->Psi4Enable[domain] = cfg->psi4enable; |
| 533 | vr_params->ImonSlope[domain] = cfg->imon_slope; |
| 534 | vr_params->ImonOffset[domain] = cfg->imon_offset; |
Patrick Rudolph | 9b5447b | 2019-12-04 13:51:00 +0100 | [diff] [blame] | 535 | |
| 536 | /* If board provided non-zero value, use it. */ |
| 537 | if (cfg->voltage_limit) |
| 538 | vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; |
| 539 | else |
| 540 | vr_params->VrVoltageLimit[domain] = get_sku_voltagelimit(domain); |
| 541 | |
| 542 | if (cfg->icc_max) |
| 543 | vr_params->IccMax[domain] = cfg->icc_max; |
| 544 | else |
| 545 | vr_params->IccMax[domain] = get_sku_icc_max(domain); |
| 546 | |
| 547 | if (cfg->ac_loadline) |
| 548 | vr_params->AcLoadline[domain] = cfg->ac_loadline; |
| 549 | else |
| 550 | vr_params->AcLoadline[domain] = get_sku_ac_dc_loadline(domain); |
| 551 | |
| 552 | if (cfg->dc_loadline) |
| 553 | vr_params->DcLoadline[domain] = cfg->dc_loadline; |
| 554 | else |
| 555 | vr_params->DcLoadline[domain] = get_sku_ac_dc_loadline(domain); |
Marx Wang | 9318d6d | 2020-02-07 16:44:14 +0800 | [diff] [blame^] | 556 | |
| 557 | vr_params->TdcEnable[domain] = !cfg->tdc_disable; |
| 558 | |
| 559 | if (cfg->tdc_powerlimit) |
| 560 | vr_params->TdcPowerLimit[domain] = cfg->tdc_powerlimit; |
| 561 | else |
| 562 | vr_params->TdcPowerLimit[domain] = get_sku_tdc_powerlimit(domain); |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 563 | } |