Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 2 | |
Elyes HAOUAS | 92f46aa | 2020-09-15 08:42:17 +0200 | [diff] [blame] | 3 | #include <arch/io.h> |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 4 | #include <stdint.h> |
| 5 | #include <console/console.h> |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 7 | #include <timestamp.h> |
| 8 | #include <romstage_handoff.h> |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 9 | #include "ironlake.h" |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 10 | #include <arch/romstage.h> |
| 11 | #include <device/pci_def.h> |
| 12 | #include <device/device.h> |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 13 | #include <northbridge/intel/ironlake/chip.h> |
| 14 | #include <northbridge/intel/ironlake/raminit.h> |
Arthur Heymans | 2878c0b | 2019-10-14 18:42:00 +0200 | [diff] [blame] | 15 | #include <southbridge/intel/common/pmclib.h> |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 16 | #include <southbridge/intel/ibexpeak/pch.h> |
| 17 | #include <southbridge/intel/ibexpeak/me.h> |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 18 | |
Angel Pons | 43bcc7b | 2020-06-22 18:11:31 +0200 | [diff] [blame] | 19 | /* |
| 20 | * Platform has no romstage entry point under mainboard directory, |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 21 | * so this one is named with prefix mainboard. |
| 22 | */ |
| 23 | void mainboard_romstage_entry(void) |
| 24 | { |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 25 | int s3resume = 0; |
| 26 | u8 spd_addrmap[4] = {}; |
| 27 | |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 28 | /* TODO, make this configurable */ |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 29 | ironlake_early_initialization(IRONLAKE_MOBILE); |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 30 | |
Arthur Heymans | b9c9cd7 | 2019-10-10 15:06:33 +0200 | [diff] [blame] | 31 | early_pch_init(); |
| 32 | |
Arthur Heymans | 2878c0b | 2019-10-14 18:42:00 +0200 | [diff] [blame] | 33 | s3resume = southbridge_detect_s3_resume(); |
| 34 | if (s3resume) { |
| 35 | u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 36 | if (!(reg8 & 0x20)) { |
Arthur Heymans | 2878c0b | 2019-10-14 18:42:00 +0200 | [diff] [blame] | 37 | s3resume = 0; |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 38 | printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 39 | } |
| 40 | } |
| 41 | |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 42 | early_thermal_init(); |
| 43 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 44 | timestamp_add_now(TS_INITRAM_START); |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 45 | |
| 46 | chipset_init(s3resume); |
| 47 | |
| 48 | mainboard_pre_raminit(); |
| 49 | |
| 50 | mainboard_get_spd_map(spd_addrmap); |
| 51 | |
| 52 | raminit(s3resume, spd_addrmap); |
| 53 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 54 | timestamp_add_now(TS_INITRAM_END); |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 55 | |
| 56 | intel_early_me_status(); |
| 57 | |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 58 | romstage_handoff_init(s3resume); |
| 59 | } |