Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 3 | |
| 4 | #include <stdint.h> |
| 5 | #include <console/console.h> |
| 6 | #include <cf9_reset.h> |
| 7 | #include <device/pci_ops.h> |
| 8 | #include <cpu/x86/lapic.h> |
| 9 | #include <timestamp.h> |
| 10 | #include <romstage_handoff.h> |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 11 | #include "ironlake.h" |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 12 | #include <arch/romstage.h> |
| 13 | #include <device/pci_def.h> |
| 14 | #include <device/device.h> |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 15 | #include <northbridge/intel/ironlake/chip.h> |
| 16 | #include <northbridge/intel/ironlake/raminit.h> |
Arthur Heymans | 2878c0b | 2019-10-14 18:42:00 +0200 | [diff] [blame] | 17 | #include <southbridge/intel/common/pmclib.h> |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 18 | #include <southbridge/intel/ibexpeak/pch.h> |
| 19 | #include <southbridge/intel/ibexpeak/me.h> |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 20 | |
| 21 | /* Platform has no romstage entry point under mainboard directory, |
| 22 | * so this one is named with prefix mainboard. |
| 23 | */ |
| 24 | void mainboard_romstage_entry(void) |
| 25 | { |
| 26 | u32 reg32; |
| 27 | int s3resume = 0; |
| 28 | u8 spd_addrmap[4] = {}; |
| 29 | |
| 30 | enable_lapic(); |
| 31 | |
| 32 | /* TODO, make this configurable */ |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 33 | ironlake_early_initialization(IRONLAKE_MOBILE); |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 34 | |
Arthur Heymans | b9c9cd7 | 2019-10-10 15:06:33 +0200 | [diff] [blame] | 35 | early_pch_init(); |
| 36 | |
Arthur Heymans | 2878c0b | 2019-10-14 18:42:00 +0200 | [diff] [blame] | 37 | s3resume = southbridge_detect_s3_resume(); |
| 38 | if (s3resume) { |
| 39 | u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 40 | if (!(reg8 & 0x20)) { |
Arthur Heymans | 2878c0b | 2019-10-14 18:42:00 +0200 | [diff] [blame] | 41 | s3resume = 0; |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 42 | printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 43 | } |
| 44 | } |
| 45 | |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 46 | early_thermal_init(); |
| 47 | |
| 48 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 49 | |
| 50 | chipset_init(s3resume); |
| 51 | |
| 52 | mainboard_pre_raminit(); |
| 53 | |
| 54 | mainboard_get_spd_map(spd_addrmap); |
| 55 | |
| 56 | raminit(s3resume, spd_addrmap); |
| 57 | |
| 58 | timestamp_add_now(TS_AFTER_INITRAM); |
| 59 | |
| 60 | intel_early_me_status(); |
| 61 | |
| 62 | if (s3resume) { |
| 63 | /* Clear SLP_TYPE. This will break stage2 but |
| 64 | * we care for that when we get there. |
| 65 | */ |
| 66 | reg32 = inl(DEFAULT_PMBASE + 0x04); |
| 67 | outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); |
| 68 | } |
| 69 | |
| 70 | romstage_handoff_init(s3resume); |
| 71 | } |