Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2 | |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 3 | #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ |
| 4 | #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 5 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 6 | /* |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 7 | * D1:F0 PEG |
| 8 | */ |
Angel Pons | dd6a3d8 | 2020-06-22 17:21:23 +0200 | [diff] [blame] | 9 | #define PEG_CAP 0xa2 |
| 10 | #define SLOTCAP 0xb4 |
| 11 | #define PEGLC 0xec |
| 12 | #define D1F0_VCCAP 0x104 |
| 13 | #define D1F0_VC0RCTL 0x114 |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 14 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 15 | /* Chipset types */ |
Angel Pons | dd6a3d8 | 2020-06-22 17:21:23 +0200 | [diff] [blame] | 16 | #define IRONLAKE_MOBILE 0 |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 17 | #define IRONLAKE_DESKTOP 1 |
Angel Pons | dd6a3d8 | 2020-06-22 17:21:23 +0200 | [diff] [blame] | 18 | #define IRONLAKE_SERVER 2 |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 19 | |
Angel Pons | cdd9db3 | 2020-09-15 00:11:27 +0200 | [diff] [blame] | 20 | #include "memmap.h" |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 21 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 22 | #define QUICKPATH_BUS (CONFIG_ECAM_MMCONF_BUS_NUMBER - 1) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 23 | |
| 24 | #include <southbridge/intel/ibexpeak/pch.h> |
| 25 | |
| 26 | /* Everything below this line is ignored in the DSDT */ |
| 27 | #ifndef __ACPI__ |
| 28 | |
| 29 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
| 30 | |
Angel Pons | 35a7742 | 2020-09-15 00:31:26 +0200 | [diff] [blame] | 31 | #include "registers/host_bridge.h" |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 32 | |
Angel Pons | e9d1d70 | 2020-07-22 12:47:00 +0200 | [diff] [blame] | 33 | /* |
Angel Pons | c642a0d | 2020-07-22 18:21:43 +0200 | [diff] [blame] | 34 | * Generic Non-Core Registers |
| 35 | */ |
| 36 | #define QPI_NON_CORE PCI_DEV(QUICKPATH_BUS, 0, 0) |
| 37 | |
Angel Pons | 9addda3 | 2020-07-22 18:37:32 +0200 | [diff] [blame] | 38 | #define MAX_RTIDS 0x60 |
| 39 | #define DESIRED_CORES 0x80 |
| 40 | #define MIRROR_PORT_CTL 0xd0 |
| 41 | |
Angel Pons | c642a0d | 2020-07-22 18:21:43 +0200 | [diff] [blame] | 42 | /* |
Angel Pons | 3ab19b3 | 2020-07-22 16:29:54 +0200 | [diff] [blame] | 43 | * SAD - System Address Decoder |
Angel Pons | e9d1d70 | 2020-07-22 12:47:00 +0200 | [diff] [blame] | 44 | */ |
Angel Pons | 3ab19b3 | 2020-07-22 16:29:54 +0200 | [diff] [blame] | 45 | #define QPI_SAD PCI_DEV(QUICKPATH_BUS, 0, 1) |
| 46 | |
Angel Pons | e9d1d70 | 2020-07-22 12:47:00 +0200 | [diff] [blame] | 47 | #define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ |
Vladimir Serbinenko | 786c0f5 | 2014-01-02 10:16:46 +0100 | [diff] [blame] | 48 | #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 49 | |
Angel Pons | 4500893 | 2020-07-22 16:43:48 +0200 | [diff] [blame] | 50 | #define SAD_PCIEXBAR 0x50 |
| 51 | |
Angel Pons | 6757337 | 2020-07-22 16:56:00 +0200 | [diff] [blame] | 52 | #define SAD_DRAM_RULE(x) (0x80 + 4 * (x)) /* 0-7 */ |
| 53 | #define SAD_INTERLEAVE_LIST(x) (0xc0 + 4 * (x)) /* 0-7 */ |
| 54 | |
Angel Pons | 93d9517 | 2020-07-22 17:30:49 +0200 | [diff] [blame] | 55 | /* |
| 56 | * QPI Link 0 |
| 57 | */ |
| 58 | #define QPI_LINK_0 PCI_DEV(QUICKPATH_BUS, 2, 0) |
| 59 | |
Angel Pons | 0814357 | 2020-07-22 17:47:06 +0200 | [diff] [blame] | 60 | #define QPI_QPILCP 0x40 /* QPI Link Capability */ |
| 61 | #define QPI_QPILCL 0x48 /* QPI Link Control */ |
| 62 | #define QPI_QPILS 0x50 /* QPI Link Status */ |
| 63 | #define QPI_DEF_RMT_VN_CREDITS 0x58 /* Default Available Remote Credits */ |
| 64 | |
Angel Pons | 10993c4 | 2020-07-22 17:49:28 +0200 | [diff] [blame] | 65 | /* |
| 66 | * QPI Physical Layer 0 |
| 67 | */ |
| 68 | #define QPI_PHY_0 PCI_DEV(QUICKPATH_BUS, 2, 1) |
| 69 | |
Angel Pons | a457e35 | 2020-07-22 18:17:33 +0200 | [diff] [blame] | 70 | #define QPI_PLL_STATUS 0x50 |
| 71 | #define QPI_PLL_RATIO 0x54 |
| 72 | #define QPI_PHY_CAPABILITY 0x68 /* QPI Phys. Layer Capability */ |
| 73 | #define QPI_PHY_CONTROL 0x6c /* QPI Phys. Layer Control */ |
| 74 | #define QPI_PHY_INIT_STATUS 0x80 /* QPI Phys. Layer Initialization Status */ |
| 75 | #define QPI_PHY_PRIM_TIMEOUT 0x94 /* QPI Phys. Layer Primary Timeout Value */ |
| 76 | #define QPI_PHY_PWR_MGMT 0xd0 /* QPI Phys. Layer Power Management */ |
| 77 | #define QPI_PHY_EP_SELECT 0xe0 /* QPI Phys. Layer Electrical Parameter Select */ |
| 78 | #define QPI_PHY_EP_MCTR 0xf4 /* QPI Phys. Layer Electrical Parameter Misc. Control */ |
| 79 | |
Angel Pons | cdd9db3 | 2020-09-15 00:11:27 +0200 | [diff] [blame] | 80 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 81 | /* Device 0:2.0 PCI configuration space (Graphics Device) */ |
| 82 | |
| 83 | #define MSAC 0x62 /* Multi Size Aperture Control */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 84 | |
| 85 | /* |
| 86 | * MCHBAR |
| 87 | */ |
| 88 | |
Angel Pons | a8df6cf | 2021-01-20 01:32:17 +0100 | [diff] [blame] | 89 | #include <northbridge/intel/common/fixed_bars.h> |
| 90 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 91 | /* |
| 92 | * EPBAR - Egress Port Root Complex Register Block |
| 93 | */ |
| 94 | |
Angel Pons | 5876998 | 2020-09-15 00:36:15 +0200 | [diff] [blame] | 95 | #include "registers/epbar.h" |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 96 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 97 | /* |
| 98 | * DMIBAR |
| 99 | */ |
| 100 | |
Angel Pons | 5876998 | 2020-09-15 00:36:15 +0200 | [diff] [blame] | 101 | #include "registers/dmibar.h" |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 102 | |
| 103 | #ifndef __ASSEMBLER__ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 104 | |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 105 | void intel_ironlake_finalize_smm(void); |
Kyösti Mälkki | 82c0e7e | 2019-11-05 19:06:56 +0200 | [diff] [blame] | 106 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 107 | int bridge_silicon_revision(void); |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 108 | void ironlake_early_initialization(int chipset_type); |
| 109 | void ironlake_late_initialization(void); |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 110 | void mainboard_pre_raminit(void); |
| 111 | void mainboard_get_spd_map(u8 *spd_addrmap); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 112 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 113 | #endif |
| 114 | #endif |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 115 | #endif /* __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ */ |