commit a8df6cff16d4f24a7f6dfedd5979d0948ddda189
author Angel Pons <th3fanbus@gmail.com> Wed Jan 20 01:32:17 2021 +0100
committer Patrick Georgi <pgeorgi@google.com> Wed Feb 10 07:29:29 2021 +0000
tree 949d112b6fb9ec868200dfb57869d2f3b0fb6b59
parent d9e58dca9e72ca2efa62eab832aad606c9c58fcd

nb/intel/ironlake: Use common {DMI,EP,MCH}BAR accessors

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I166dbebf0eaf9fe0454145d4d48a0622743916fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/northbridge/intel/ironlake/ironlake.h

diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h
index 3a61253..cfa16a6 100644
--- a/src/northbridge/intel/ironlake/ironlake.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -88,9 +88,8 @@
  * MCHBAR
  */
 
-#define MCHBAR8(x)			(*((volatile u8  *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR16(x)			(*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR32(x)			(*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
+#include <northbridge/intel/common/fixed_bars.h>
+
 #define MCHBAR8_AND(x,  and)		(MCHBAR8(x)  = MCHBAR8(x)  & (and))
 #define MCHBAR16_AND(x, and)		(MCHBAR16(x) = MCHBAR16(x) & (and))
 #define MCHBAR32_AND(x, and)		(MCHBAR32(x) = MCHBAR32(x) & (and))
@@ -104,20 +103,12 @@
  * EPBAR - Egress Port Root Complex Register Block
  */
 
-#define EPBAR8(x)	(*((volatile u8  *)(DEFAULT_EPBAR + (x))))
-#define EPBAR16(x)	(*((volatile u16 *)(DEFAULT_EPBAR + (x))))
-#define EPBAR32(x)	(*((volatile u32 *)(DEFAULT_EPBAR + (x))))
-
 #include "registers/epbar.h"
 
 /*
  * DMIBAR
  */
 
-#define DMIBAR8(x)	(*((volatile u8  *)(DEFAULT_DMIBAR + (x))))
-#define DMIBAR16(x)	(*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
-#define DMIBAR32(x)	(*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
-
 #include "registers/dmibar.h"
 
 #ifndef __ASSEMBLER__