| commit | c642a0d8942735b393040b877769f1d4a3a9ebe8 | [log] [tgz] |
|---|---|---|
| author | Angel Pons <th3fanbus@gmail.com> | Wed Jul 22 18:21:43 2020 +0200 |
| committer | Patrick Georgi <pgeorgi@google.com> | Mon Aug 03 05:32:12 2020 +0000 |
| tree | cf118ea9fd286c47bed111a309f23e47c99cba65 | |
| parent | a457e352374e0efe4944bd1c81a3ca8ffd65b750 [diff] [blame] |
nb/intel/ironlake: Add Generic Non-Core PCI device definition Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I8feff0d71ad70ac994e29b238d35e2c73aa92ecd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 06e0771..4f9db5b 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -48,6 +48,11 @@ #include "hostbridge_regs.h" /* + * Generic Non-Core Registers + */ +#define QPI_NON_CORE PCI_DEV(QUICKPATH_BUS, 0, 0) + +/* * SAD - System Address Decoder */ #define QPI_SAD PCI_DEV(QUICKPATH_BUS, 0, 1)