Blame - src/southbridge/amd/pi/hudson/pci_devs.h - coreboot

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Angel Pons	182dbde	2020-04-02 23:49:05 +0200	[diff] [blame]	1	/* SPDX-License-Identifier: GPL-2.0-only */
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	2
				3	#ifndef _PI_HUDSON_PCI_DEVS_H_
				4	#define _PI_HUDSON_PCI_DEVS_H_
				5
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	6	#include <device/pci_def.h>
				7
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	8	#define BUS0 0
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	9
				10	/* XHCI */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	11	#define XHCI_DEV 0x10
				12	#define XHCI_FUNC 0
				13	#define XHCI_DEVID 0x7814
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	14	#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	15
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	16	#define XHCI2_DEV 0x10
				17	#define XHCI2_FUNC 1
				18	#define XHCI2_DEVID 0x7814
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	19	#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC)
Dave Frodin	9cfa742	2015-01-27 07:19:48 -0700	[diff] [blame]	20
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	21	/* SATA */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	22	#define SATA_DEV 0x11
				23	#define SATA_FUNC 0
				24	#define SATA_IDE_DEVID 0x7800
				25	#define AHCI_DEVID_MS 0x7801
				26	#define AHCI_DEVID_AMD 0x7804
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	27	#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	28
				29	/* OHCI */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	30	#define OHCI1_DEV 0x12
				31	#define OHCI1_FUNC 0
				32	#define OHCI2_DEV 0x13
				33	#define OHCI2_FUNC 0
				34	#define OHCI3_DEV 0x16
				35	#define OHCI3_FUNC 0
				36	#define OHCI4_DEV 0x14
				37	#define OHCI4_FUNC 5
				38	#define OHCI_DEVID 0x7807
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	39	#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC)
				40	#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC)
				41	#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC)
				42	#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	43
				44	/* EHCI */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	45	#define EHCI1_DEV 0x12
				46	#define EHCI1_FUNC 2
				47	#define EHCI2_DEV 0x13
				48	#define EHCI2_FUNC 2
				49	#define EHCI3_DEV 0x16
				50	#define EHCI3_FUNC 2
				51	#define EHCI_DEVID 0x7808
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	52	#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC)
				53	#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC)
				54	#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	55
				56	/* SMBUS */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	57	#define SMBUS_DEV 0x14
				58	#define SMBUS_FUNC 0
				59	#define SMBUS_DEVID 0x780B
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	60	#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	61
				62	/* HD Audio */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	63	#define HDA_DEV 0x14
				64	#define HDA_FUNC 2
				65	#define HDA_DEVID 0x780D
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	66	#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	67
				68	/* LPC BUS */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	69	#define PCU_DEV 0x14
Philipp Deppenwiese	3067012	2017-03-01 02:24:33 +0100	[diff] [blame]	70	#define LPC_DEV PCU_DEV
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	71	#define LPC_FUNC 3
				72	#define LPC_DEVID 0x780E
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	73	#define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	74
				75	/* PCI Ports */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	76	#define SB_PCI_PORT_DEV 0x14
				77	#define SB_PCI_PORT_FUNC 4
				78	#define SB_PCI_PORT_DEVID 0x780F
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	79	#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	80
				81	/* SD Controller */
Marshall Dawson	c1f3233	2017-04-21 13:54:08 -0600	[diff] [blame]	82	#define SD_DEV 0x14
				83	#define SD_FUNC 7
				84	#define SD_DEVID 0x7806
Elyes HAOUAS	8ccc8fd	2020-10-01 10:59:56 +0200	[diff] [blame]	85	#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC)
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	86
Kyösti Mälkki	e8b4da2	2014-10-21 18:22:32 +0300	[diff] [blame]	87	#endif /* _PI_HUDSON_PCI_DEVS_H_ */