Elyes HAOUAS | 674ad92 | 2020-05-09 13:21:47 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-or-later |
Arthur Heymans | a1e46ae | 2018-12-15 18:26:05 +0100 | [diff] [blame] | 2 | |
| 3 | chip northbridge/intel/x4x # Northbridge |
Arthur Heymans | 1eecb8c | 2022-11-07 10:04:56 +0100 | [diff] [blame] | 4 | device cpu_cluster 0 on |
| 5 | ops x4x_cpu_bus_ops # APIC cluster |
Arthur Heymans | a1e46ae | 2018-12-15 18:26:05 +0100 | [diff] [blame] | 6 | chip cpu/intel/socket_LGA775 |
| 7 | device lapic 0 on end |
| 8 | end |
Arthur Heymans | a1e46ae | 2018-12-15 18:26:05 +0100 | [diff] [blame] | 9 | end |
Arthur Heymans | 1eecb8c | 2022-11-07 10:04:56 +0100 | [diff] [blame] | 10 | device domain 0 on |
| 11 | ops x4x_pci_domain_ops # PCI domain |
Arthur Heymans | a1e46ae | 2018-12-15 18:26:05 +0100 | [diff] [blame] | 12 | subsystemid 0x17aa 0x304f inherit |
| 13 | device pci 0.0 on end # Host Bridge |
| 14 | device pci 1.0 on end # PEG |
| 15 | device pci 2.0 on end # Integrated graphics controller |
| 16 | chip southbridge/intel/i82801gx # Southbridge |
| 17 | register "pirqa_routing" = "0x0b" |
| 18 | register "pirqb_routing" = "0x0b" |
| 19 | register "pirqc_routing" = "0x0b" |
| 20 | register "pirqd_routing" = "0x0b" |
| 21 | register "pirqe_routing" = "0x80" |
| 22 | register "pirqf_routing" = "0x80" |
| 23 | register "pirqg_routing" = "0x80" |
| 24 | register "pirqh_routing" = "0x0b" |
| 25 | # GPI routing |
| 26 | # 0 No effect (default) |
| 27 | # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 28 | # 2 SCI (if corresponding GPIO_EN bit is also set) |
| 29 | register "gpi13_routing" = "1" # ??vendor |
| 30 | |
Elyes Haouas | dc3beea | 2022-11-29 17:36:51 +0100 | [diff] [blame] | 31 | register "ide_enable_primary" = "true" |
Arthur Heymans | a1e46ae | 2018-12-15 18:26:05 +0100 | [diff] [blame] | 32 | register "gpe0_en" = "0x440" |
| 33 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 34 | register "gen1_dec" = "0x00fc0a01" |
| 35 | |
Arthur Heymans | a1e46ae | 2018-12-15 18:26:05 +0100 | [diff] [blame] | 36 | device pci 1b.0 on end # Audio |
| 37 | device pci 1c.0 on end # PCIe 1 |
| 38 | device pci 1c.1 on # PCIe 2: NIC |
Peter Lemenkov | 4ed2598 | 2020-02-06 14:51:27 +0100 | [diff] [blame] | 39 | device pci 00.0 on end |
Arthur Heymans | a1e46ae | 2018-12-15 18:26:05 +0100 | [diff] [blame] | 40 | end |
| 41 | device pci 1c.2 off end # PCIe 3 |
| 42 | device pci 1c.3 off end # PCIe 4 |
Arthur Heymans | a1e46ae | 2018-12-15 18:26:05 +0100 | [diff] [blame] | 43 | device pci 1d.0 on end # USB |
| 44 | device pci 1d.1 on end # USB |
| 45 | device pci 1d.2 on end # USB |
| 46 | device pci 1d.3 on end # USB |
| 47 | device pci 1d.7 on end # USB |
| 48 | device pci 1e.0 on end # PCI bridge |
| 49 | device pci 1e.2 off end # AC'97 Audio Controller |
| 50 | device pci 1e.3 off end # AC'97 Modem Controller |
| 51 | device pci 1f.0 on # LPC bridge |
| 52 | chip superio/smsc/smscsuperio |
| 53 | device pnp 2e.0 off end # Floppy |
| 54 | device pnp 2e.3 on # Parallel Port |
| 55 | io 0x60 = 0x378 |
| 56 | irq 0x70 = 7 |
| 57 | drq 0x74 = 3 |
| 58 | end |
| 59 | device pnp 2e.4 on # COM1 |
| 60 | io 0x60 = 0x3f8 |
| 61 | irq 0x70 = 4 |
| 62 | end |
| 63 | device pnp 2e.5 off end # COM2 |
| 64 | device pnp 2e.7 on # Keyboard |
| 65 | io 0x60 = 0x60 # Can't read this back |
| 66 | io 0x62 = 0x64 # Can't read this back |
| 67 | irq 0x70 = 1 |
| 68 | irq 0x72 = 12 |
| 69 | end |
| 70 | device pnp 2e.a on # Runtime Regs |
| 71 | io 0x60 = 0x0a00 |
| 72 | end |
| 73 | end # smscsuperio |
| 74 | end |
| 75 | device pci 1f.1 on end # PATA/IDE |
| 76 | device pci 1f.2 on end # SATA |
| 77 | device pci 1f.3 on # SMbus |
| 78 | chip drivers/i2c/at24rf08c |
| 79 | device i2c 54 on end |
| 80 | device i2c 55 on end |
| 81 | device i2c 56 on end |
| 82 | device i2c 57 on end |
| 83 | end |
| 84 | chip drivers/i2c/ck505 |
| 85 | register "mask" = "{ 0x00, 0x80 }" |
| 86 | register "regs" = "{ 0x00, 0x80 }" |
| 87 | device i2c 69 on end |
| 88 | end |
| 89 | end |
| 90 | end |
| 91 | end |
| 92 | end |