src/mainboard/lenovo/thinkcentre_a58/devicetree.cb

#
# This file is part of the coreboot project.
#
# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#

chip northbridge/intel/x4x		# Northbridge
	device cpu_cluster 0 on		# APIC cluster
		chip cpu/intel/socket_LGA775
			device lapic 0 on end
		end
		chip cpu/intel/model_1067x		# CPU
			device lapic 0xACAC off end
		end
	end
	device domain 0 on		# PCI domain
		subsystemid 0x17aa 0x304f inherit
		device pci 0.0 on end			# Host Bridge
		device pci 1.0 on end			# PEG
		device pci 2.0 on end			# Integrated graphics controller
		chip southbridge/intel/i82801gx	# Southbridge
			register "pirqa_routing" = "0x0b"
			register "pirqb_routing" = "0x0b"
			register "pirqc_routing" = "0x0b"
			register "pirqd_routing" = "0x0b"
			register "pirqe_routing" = "0x80"
			register "pirqf_routing" = "0x80"
			register "pirqg_routing" = "0x80"
			register "pirqh_routing" = "0x0b"
			# GPI routing
			#  0 No effect (default)
			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
			#  2 SCI (if corresponding GPIO_EN bit is also set)
			register "gpi13_routing" = "1" # ??vendor

			register "ide_enable_primary" = "0x1"
			register "gpe0_en" = "0x440"

			register "gen1_dec" = "0x00fc0a01"

			device pci 1b.0 on end		# Audio
			device pci 1c.0 on end		# PCIe 1
			device pci 1c.1 on		# PCIe 2: NIC
				device pci 00.0 on end
			end
			device pci 1c.2 off end		# PCIe 3
			device pci 1c.3 off end		# PCIe 4
			device pci 1d.0 on end		# USB
			device pci 1d.1 on end		# USB
			device pci 1d.2 on end		# USB
			device pci 1d.3 on end		# USB
			device pci 1d.7 on end		# USB
			device pci 1e.0 on end		# PCI bridge
			device pci 1e.2 off end		# AC'97 Audio Controller
			device pci 1e.3 off end		# AC'97 Modem Controller
			device pci 1f.0 on		# LPC bridge
				chip superio/smsc/smscsuperio
					device pnp 2e.0 off end		# Floppy
					device pnp 2e.3 on		# Parallel Port
						io 0x60 = 0x378
						irq 0x70 = 7
						drq 0x74 = 3
					end
					device pnp 2e.4 on		# COM1
						io 0x60 = 0x3f8
						irq 0x70 = 4
					end
					device pnp 2e.5 off end		# COM2
					device pnp 2e.7 on		# Keyboard
						io 0x60 = 0x60 # Can't read this back
						io 0x62 = 0x64 # Can't read this back
						irq 0x70 = 1
						irq 0x72 = 12
					end
					device pnp 2e.a on		# Runtime Regs
						io 0x60 = 0x0a00
					end
				end # smscsuperio
			end
			device pci 1f.1 on end	# PATA/IDE
			device pci 1f.2 on end	# SATA
			device pci 1f.3 on	# SMbus
				chip drivers/i2c/at24rf08c
					device i2c 54 on end
					device i2c 55 on end
					device i2c 56 on end
					device i2c 57 on end
				end
				chip drivers/i2c/ck505
					register "mask" = "{ 0x00, 0x80 }"
					register "regs" = "{ 0x00, 0x80 }"
					device i2c 69 on end
				end
			end
		end
	end
end