Arthur Heymans | a1e46ae | 2018-12-15 18:26:05 +0100 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz> |
| 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; either version 2 of the License, or |
| 9 | # (at your option) any later version. |
| 10 | # |
| 11 | # This program is distributed in the hope that it will be useful, |
| 12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | # GNU General Public License for more details. |
| 15 | # |
| 16 | |
| 17 | chip northbridge/intel/x4x # Northbridge |
| 18 | device cpu_cluster 0 on # APIC cluster |
| 19 | chip cpu/intel/socket_LGA775 |
| 20 | device lapic 0 on end |
| 21 | end |
| 22 | chip cpu/intel/model_1067x # CPU |
| 23 | device lapic 0xACAC off end |
| 24 | end |
| 25 | end |
| 26 | device domain 0 on # PCI domain |
| 27 | subsystemid 0x17aa 0x304f inherit |
| 28 | device pci 0.0 on end # Host Bridge |
| 29 | device pci 1.0 on end # PEG |
| 30 | device pci 2.0 on end # Integrated graphics controller |
| 31 | chip southbridge/intel/i82801gx # Southbridge |
| 32 | register "pirqa_routing" = "0x0b" |
| 33 | register "pirqb_routing" = "0x0b" |
| 34 | register "pirqc_routing" = "0x0b" |
| 35 | register "pirqd_routing" = "0x0b" |
| 36 | register "pirqe_routing" = "0x80" |
| 37 | register "pirqf_routing" = "0x80" |
| 38 | register "pirqg_routing" = "0x80" |
| 39 | register "pirqh_routing" = "0x0b" |
| 40 | # GPI routing |
| 41 | # 0 No effect (default) |
| 42 | # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 43 | # 2 SCI (if corresponding GPIO_EN bit is also set) |
| 44 | register "gpi13_routing" = "1" # ??vendor |
| 45 | |
| 46 | register "ide_enable_primary" = "0x1" |
Arthur Heymans | a1e46ae | 2018-12-15 18:26:05 +0100 | [diff] [blame] | 47 | register "gpe0_en" = "0x440" |
| 48 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 49 | register "gen1_dec" = "0x00fc0a01" |
| 50 | |
Arthur Heymans | a1e46ae | 2018-12-15 18:26:05 +0100 | [diff] [blame] | 51 | device pci 1b.0 on end # Audio |
| 52 | device pci 1c.0 on end # PCIe 1 |
| 53 | device pci 1c.1 on # PCIe 2: NIC |
Peter Lemenkov | 4ed2598 | 2020-02-06 14:51:27 +0100 | [diff] [blame^] | 54 | device pci 00.0 on end |
Arthur Heymans | a1e46ae | 2018-12-15 18:26:05 +0100 | [diff] [blame] | 55 | end |
| 56 | device pci 1c.2 off end # PCIe 3 |
| 57 | device pci 1c.3 off end # PCIe 4 |
Arthur Heymans | a1e46ae | 2018-12-15 18:26:05 +0100 | [diff] [blame] | 58 | device pci 1d.0 on end # USB |
| 59 | device pci 1d.1 on end # USB |
| 60 | device pci 1d.2 on end # USB |
| 61 | device pci 1d.3 on end # USB |
| 62 | device pci 1d.7 on end # USB |
| 63 | device pci 1e.0 on end # PCI bridge |
| 64 | device pci 1e.2 off end # AC'97 Audio Controller |
| 65 | device pci 1e.3 off end # AC'97 Modem Controller |
| 66 | device pci 1f.0 on # LPC bridge |
| 67 | chip superio/smsc/smscsuperio |
| 68 | device pnp 2e.0 off end # Floppy |
| 69 | device pnp 2e.3 on # Parallel Port |
| 70 | io 0x60 = 0x378 |
| 71 | irq 0x70 = 7 |
| 72 | drq 0x74 = 3 |
| 73 | end |
| 74 | device pnp 2e.4 on # COM1 |
| 75 | io 0x60 = 0x3f8 |
| 76 | irq 0x70 = 4 |
| 77 | end |
| 78 | device pnp 2e.5 off end # COM2 |
| 79 | device pnp 2e.7 on # Keyboard |
| 80 | io 0x60 = 0x60 # Can't read this back |
| 81 | io 0x62 = 0x64 # Can't read this back |
| 82 | irq 0x70 = 1 |
| 83 | irq 0x72 = 12 |
| 84 | end |
| 85 | device pnp 2e.a on # Runtime Regs |
| 86 | io 0x60 = 0x0a00 |
| 87 | end |
| 88 | end # smscsuperio |
| 89 | end |
| 90 | device pci 1f.1 on end # PATA/IDE |
| 91 | device pci 1f.2 on end # SATA |
| 92 | device pci 1f.3 on # SMbus |
| 93 | chip drivers/i2c/at24rf08c |
| 94 | device i2c 54 on end |
| 95 | device i2c 55 on end |
| 96 | device i2c 56 on end |
| 97 | device i2c 57 on end |
| 98 | end |
| 99 | chip drivers/i2c/ck505 |
| 100 | register "mask" = "{ 0x00, 0x80 }" |
| 101 | register "regs" = "{ 0x00, 0x80 }" |
| 102 | device i2c 69 on end |
| 103 | end |
| 104 | end |
| 105 | end |
| 106 | end |
| 107 | end |