Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2 | |
Arthur Heymans | 022d235 | 2022-05-06 12:10:39 +0200 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
| 4 | #include <acpi/acpigen.h> |
| 5 | #include <boot/tables.h> |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 6 | #include <cbmem.h> |
Angel Pons | b9bbed2 | 2020-08-03 15:11:55 +0200 | [diff] [blame] | 7 | #include <commonlib/helpers.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 8 | #include <console/console.h> |
Arthur Heymans | 022d235 | 2022-05-06 12:10:39 +0200 | [diff] [blame] | 9 | #include <cpu/cpu.h> |
| 10 | #include <cpu/intel/smm_reloc.h> |
| 11 | #include <device/device.h> |
Elyes HAOUAS | 748caed | 2019-12-19 17:02:08 +0100 | [diff] [blame] | 12 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 13 | #include <device/pci_ops.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 14 | #include <stdint.h> |
Elyes HAOUAS | a1e22b8 | 2019-03-18 22:49:36 +0100 | [diff] [blame] | 15 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 16 | #include "chip.h" |
| 17 | #include "gm45.h" |
| 18 | |
Arthur Heymans | 022d235 | 2022-05-06 12:10:39 +0200 | [diff] [blame] | 19 | static uint64_t get_touud(void) |
| 20 | { |
| 21 | uint64_t touud = pci_read_config16(__pci_0_00_0, D0F0_TOUUD); |
| 22 | touud <<= 20; |
| 23 | return touud; |
| 24 | } |
| 25 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 26 | static void mch_domain_read_resources(struct device *dev) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 27 | { |
| 28 | u64 tom, touud; |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 29 | u32 tomk, tolud, uma_sizek = 0, delta_cbmem; |
Kyösti Mälkki | c1d4d0b | 2021-06-26 19:09:05 +0300 | [diff] [blame] | 30 | int idx = 3; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 31 | |
| 32 | /* Total Memory 2GB example: |
| 33 | * |
| 34 | * 00000000 0000MB-2014MB 2014MB RAM (writeback) |
| 35 | * 7de00000 2014MB-2016MB 2MB GFX GTT (uncached) |
| 36 | * 7e000000 2016MB-2048MB 32MB GFX UMA (uncached) |
| 37 | * 80000000 2048MB TOLUD |
| 38 | * 80000000 2048MB TOM |
| 39 | * |
| 40 | * Total Memory 4GB example: |
| 41 | * |
| 42 | * 00000000 0000MB-3038MB 3038MB RAM (writeback) |
| 43 | * bde00000 3038MB-3040MB 2MB GFX GTT (uncached) |
| 44 | * be000000 3040MB-3072MB 32MB GFX UMA (uncached) |
| 45 | * be000000 3072MB TOLUD |
| 46 | * 100000000 4096MB TOM |
| 47 | * 100000000 4096MB-5120MB 1024MB RAM (writeback) |
| 48 | * 140000000 5120MB TOUUD |
| 49 | */ |
| 50 | |
| 51 | pci_domain_read_resources(dev); |
| 52 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 53 | struct device *mch = pcidev_on_root(0, 0); |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 54 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 55 | /* Top of Upper Usable DRAM, including remap */ |
Arthur Heymans | 022d235 | 2022-05-06 12:10:39 +0200 | [diff] [blame] | 56 | touud = get_touud(); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 57 | |
| 58 | /* Top of Lower Usable DRAM */ |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 59 | tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 60 | tolud <<= 16; |
| 61 | |
| 62 | /* Top of Memory - does not account for any UMA */ |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 63 | tom = pci_read_config16(mch, D0F0_TOM) & 0x1ff; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 64 | tom <<= 27; |
| 65 | |
| 66 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", |
| 67 | touud, tolud, tom); |
| 68 | |
| 69 | tomk = tolud >> 10; |
| 70 | |
| 71 | /* Graphics memory comes next */ |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 72 | const u16 ggc = pci_read_config16(mch, D0F0_GGC); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 73 | if (!(ggc & 2)) { |
| 74 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
| 75 | |
| 76 | /* Graphics memory */ |
| 77 | const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); |
Arthur Heymans | 8b76605 | 2018-01-24 23:25:13 +0100 | [diff] [blame] | 78 | printk(BIOS_DEBUG, "%uM UMA, ", gms_sizek >> 10); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 79 | tomk -= gms_sizek; |
| 80 | |
| 81 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 82 | const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); |
Arthur Heymans | 8b76605 | 2018-01-24 23:25:13 +0100 | [diff] [blame] | 83 | printk(BIOS_DEBUG, "%uM GTT", gsm_sizek >> 10); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 84 | tomk -= gsm_sizek; |
| 85 | |
| 86 | uma_sizek = gms_sizek + gsm_sizek; |
| 87 | } |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 88 | const u8 esmramc = pci_read_config8(mch, D0F0_ESMRAMC); |
Arthur Heymans | 8b76605 | 2018-01-24 23:25:13 +0100 | [diff] [blame] | 89 | const u32 tseg_sizek = decode_tseg_size(esmramc); |
| 90 | printk(BIOS_DEBUG, " and %uM TSEG\n", tseg_sizek >> 10); |
| 91 | tomk -= tseg_sizek; |
| 92 | uma_sizek += tseg_sizek; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 93 | |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 94 | /* cbmem_top can be shifted downwards due to alignment. |
| 95 | Mark the region between cbmem_top and tomk as unusable */ |
Arthur Heymans | 98435ed | 2022-05-06 12:22:32 +0200 | [diff] [blame] | 96 | delta_cbmem = tomk - ((uintptr_t)cbmem_top() >> 10); |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 97 | tomk -= delta_cbmem; |
| 98 | uma_sizek += delta_cbmem; |
| 99 | |
| 100 | printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", |
| 101 | delta_cbmem); |
| 102 | |
Nico Huber | ca3e121 | 2017-10-02 20:07:53 +0200 | [diff] [blame] | 103 | printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 104 | |
Nico Huber | 58ba83f | 2021-01-17 21:50:55 +0100 | [diff] [blame] | 105 | /* Report lowest memory region */ |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 106 | ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); |
Nico Huber | 58ba83f | 2021-01-17 21:50:55 +0100 | [diff] [blame] | 107 | |
| 108 | /* |
| 109 | * Reserve everything between A segment and 1MB: |
| 110 | * |
| 111 | * 0xa0000 - 0xbffff: Legacy VGA |
| 112 | * 0xc0000 - 0xfffff: RAM |
| 113 | */ |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 114 | mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB); |
| 115 | reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, (1*MiB - 0xc0000) / KiB); |
Nico Huber | 58ba83f | 2021-01-17 21:50:55 +0100 | [diff] [blame] | 116 | |
| 117 | /* Report < 4GB memory */ |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 118 | ram_resource_kb(dev, idx++, 1*MiB / KiB, tomk - 1*MiB / KiB); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 119 | |
| 120 | /* |
| 121 | * If >= 4GB installed then memory from TOLUD to 4GB |
| 122 | * is remapped above TOM, TOUUD will account for both |
| 123 | */ |
Kyösti Mälkki | 0a18d64 | 2021-06-28 21:43:31 +0300 | [diff] [blame] | 124 | upper_ram_end(dev, idx++, touud); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 125 | |
| 126 | printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " |
| 127 | "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10); |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 128 | /* Don't use uma_resource_kb() as our UMA touches the PCI hole. */ |
| 129 | fixed_mem_resource_kb(dev, idx++, tomk, uma_sizek, IORESOURCE_RESERVE); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 130 | |
Kyösti Mälkki | c1d4d0b | 2021-06-26 19:09:05 +0300 | [diff] [blame] | 131 | mmconf_resource(dev, idx++); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 132 | } |
| 133 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 134 | static void mch_domain_set_resources(struct device *dev) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 135 | { |
| 136 | struct resource *resource; |
| 137 | int i; |
| 138 | |
Nico Huber | 58ba83f | 2021-01-17 21:50:55 +0100 | [diff] [blame] | 139 | for (i = 3; i <= 9; ++i) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 140 | /* Report read resources. */ |
Vladimir Serbinenko | 40412c6 | 2014-11-12 00:09:20 +0100 | [diff] [blame] | 141 | resource = probe_resource(dev, i); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 142 | if (resource) |
| 143 | report_resource_stored(dev, resource, ""); |
| 144 | } |
| 145 | |
| 146 | assign_resources(dev->link_list); |
| 147 | } |
| 148 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 149 | static void mch_domain_init(struct device *dev) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 150 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 151 | struct device *mch = pcidev_on_root(0, 0); |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 152 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 153 | /* Enable SERR */ |
Elyes HAOUAS | 5ac723e | 2020-04-29 09:09:12 +0200 | [diff] [blame] | 154 | pci_or_config16(mch, PCI_COMMAND, PCI_COMMAND_SERR); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 155 | } |
| 156 | |
Arthur Heymans | e798e6a | 2017-12-23 23:09:54 +0100 | [diff] [blame] | 157 | static const char *northbridge_acpi_name(const struct device *dev) |
| 158 | { |
| 159 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 160 | return "PCI0"; |
| 161 | |
Fabio Aiuto | 61ed4ef | 2022-09-30 14:55:53 +0200 | [diff] [blame] | 162 | if (!is_pci_dev_on_bus(dev, 0)) |
Arthur Heymans | e798e6a | 2017-12-23 23:09:54 +0100 | [diff] [blame] | 163 | return NULL; |
| 164 | |
| 165 | switch (dev->path.pci.devfn) { |
| 166 | case PCI_DEVFN(0, 0): |
| 167 | return "MCHC"; |
| 168 | } |
| 169 | |
| 170 | return NULL; |
| 171 | } |
| 172 | |
Arthur Heymans | aade90e | 2018-01-25 00:33:45 +0100 | [diff] [blame] | 173 | void northbridge_write_smram(u8 smram) |
| 174 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 175 | struct device *dev = pcidev_on_root(0, 0); |
Arthur Heymans | 48fa922 | 2018-11-19 13:08:01 +0100 | [diff] [blame] | 176 | |
Elyes Haouas | 5e6b0f0 | 2022-09-13 09:55:49 +0200 | [diff] [blame] | 177 | if (!dev) |
Arthur Heymans | 48fa922 | 2018-11-19 13:08:01 +0100 | [diff] [blame] | 178 | die("could not find pci 00:00.0!\n"); |
| 179 | |
| 180 | pci_write_config8(dev, D0F0_SMRAM, smram); |
Arthur Heymans | aade90e | 2018-01-25 00:33:45 +0100 | [diff] [blame] | 181 | } |
| 182 | |
Arthur Heymans | 022d235 | 2022-05-06 12:10:39 +0200 | [diff] [blame] | 183 | static void set_above_4g_pci(const struct device *dev) |
| 184 | { |
| 185 | const uint64_t touud = get_touud(); |
| 186 | const uint64_t len = POWER_OF_2(cpu_phys_address_size()) - touud; |
| 187 | |
| 188 | const char *scope = acpi_device_path(dev); |
| 189 | acpigen_write_scope(scope); |
| 190 | acpigen_write_name_qword("A4GB", touud); |
| 191 | acpigen_write_name_qword("A4GS", len); |
| 192 | acpigen_pop_len(); |
| 193 | |
| 194 | printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", touud, len); |
| 195 | } |
| 196 | |
| 197 | static void pci_domain_ssdt(const struct device *dev) |
| 198 | { |
| 199 | generate_cpu_entries(dev); |
| 200 | set_above_4g_pci(dev); |
| 201 | } |
| 202 | |
Arthur Heymans | 2fb6f68 | 2022-11-07 09:45:19 +0100 | [diff] [blame] | 203 | struct device_operations gm45_pci_domain_ops = { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 204 | .read_resources = mch_domain_read_resources, |
| 205 | .set_resources = mch_domain_set_resources, |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 206 | .init = mch_domain_init, |
| 207 | .scan_bus = pci_domain_scan_bus, |
Vladimir Serbinenko | 33769a5 | 2014-08-30 22:39:20 +0200 | [diff] [blame] | 208 | .write_acpi_tables = northbridge_write_acpi_tables, |
Arthur Heymans | 022d235 | 2022-05-06 12:10:39 +0200 | [diff] [blame] | 209 | .acpi_fill_ssdt = pci_domain_ssdt, |
Arthur Heymans | e798e6a | 2017-12-23 23:09:54 +0100 | [diff] [blame] | 210 | .acpi_name = northbridge_acpi_name, |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 211 | }; |
| 212 | |
Arthur Heymans | 2fb6f68 | 2022-11-07 09:45:19 +0100 | [diff] [blame] | 213 | struct device_operations gm45_cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 214 | .read_resources = noop_read_resources, |
| 215 | .set_resources = noop_set_resources, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 216 | .init = mp_cpu_bus_init, |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 217 | }; |
| 218 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 219 | static void gm45_init(void *const chip_info) |
| 220 | { |
| 221 | int dev, fn, bit_base; |
| 222 | |
Kyösti Mälkki | 98a9174 | 2018-05-21 21:29:16 +0300 | [diff] [blame] | 223 | struct device *const d0f0 = pcidev_on_root(0x0, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 224 | |
| 225 | /* Hide internal functions based on devicetree info. */ |
| 226 | for (dev = 3; dev > 0; --dev) { |
| 227 | switch (dev) { |
| 228 | case 3: /* ME */ |
| 229 | fn = 3; |
| 230 | bit_base = 6; |
| 231 | break; |
| 232 | case 2: /* IGD */ |
| 233 | fn = 1; |
| 234 | bit_base = 3; |
| 235 | break; |
| 236 | case 1: /* PEG */ |
| 237 | fn = 0; |
| 238 | bit_base = 1; |
| 239 | break; |
| 240 | } |
| 241 | for (; fn >= 0; --fn) { |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 242 | const struct device *const d = pcidev_on_root(dev, fn); |
| 243 | if (!d || d->enabled) |
| 244 | continue; |
| 245 | /* FIXME: Using bitwise ops changes the binary */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 246 | pci_write_config32(d0f0, D0F0_DEVEN, |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 247 | pci_read_config32(d0f0, D0F0_DEVEN) & ~(1 << (bit_base + fn))); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 248 | } |
| 249 | } |
| 250 | |
| 251 | const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); |
| 252 | if (!(deven & (0xf << 6))) |
| 253 | pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << 14)); |
| 254 | } |
| 255 | |
| 256 | struct chip_operations northbridge_intel_gm45_ops = { |
| 257 | CHIP_NAME("Intel GM45 Northbridge") |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 258 | .init = gm45_init, |
| 259 | }; |