Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | config SOC_AMD_CEZANNE |
| 4 | bool |
| 5 | help |
| 6 | AMD Cezanne support |
| 7 | |
| 8 | if SOC_AMD_CEZANNE |
| 9 | |
| 10 | config SOC_SPECIFIC_OPTIONS |
| 11 | def_bool y |
Raul E Rangel | 24d024a | 2021-02-12 16:07:43 -0700 | [diff] [blame] | 12 | select ACPI_SOC_NVS |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 13 | select ARCH_BOOTBLOCK_X86_32 |
| 14 | select ARCH_VERSTAGE_X86_32 |
| 15 | select ARCH_ROMSTAGE_X86_32 |
| 16 | select ARCH_RAMSTAGE_X86_32 |
Raul E Rangel | 5461662 | 2021-02-05 17:29:12 -0700 | [diff] [blame] | 17 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
Felix Held | c963499 | 2021-01-26 21:35:39 +0100 | [diff] [blame] | 18 | select FSP_COMPRESS_FSP_M_LZMA |
| 19 | select FSP_COMPRESS_FSP_S_LZMA |
Felix Held | 8602495 | 2021-02-03 23:44:28 +0100 | [diff] [blame] | 20 | select HAVE_ACPI_TABLES |
Felix Held | 44f4153 | 2020-12-09 02:01:16 +0100 | [diff] [blame] | 21 | select HAVE_CF9_RESET |
Felix Held | ee2a365 | 2021-02-09 23:43:17 +0100 | [diff] [blame] | 22 | select HAVE_SMI_HANDLER |
Felix Held | cb97734 | 2021-01-19 20:36:38 +0100 | [diff] [blame] | 23 | select IDT_IN_EVERY_STAGE |
Felix Held | 4be064a | 2020-12-08 17:21:04 +0100 | [diff] [blame] | 24 | select IOAPIC |
Felix Held | 7aacdd1 | 2021-02-10 23:27:47 +0100 | [diff] [blame] | 25 | select PARALLEL_MP |
| 26 | select PARALLEL_MP_AP_WORK |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 27 | select PLATFORM_USES_FSP2_0 |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 28 | select RESET_VECTOR_IN_RAM |
Felix Held | 7cd81b9 | 2021-02-11 14:58:08 +0100 | [diff] [blame] | 29 | select RTC |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 30 | select SOC_AMD_COMMON |
Felix Held | bb4bee85 | 2021-02-10 16:53:53 +0100 | [diff] [blame] | 31 | select SOC_AMD_COMMON_BLOCK_ACPI |
Felix Held | 64de2c1 | 2020-12-05 20:53:59 +0100 | [diff] [blame] | 32 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
Felix Held | 62ef88f | 2020-12-08 23:18:19 +0100 | [diff] [blame] | 33 | select SOC_AMD_COMMON_BLOCK_AOAC |
Felix Held | 07462ef | 2020-12-11 15:55:45 +0100 | [diff] [blame] | 34 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
Felix Held | ea32c52 | 2021-02-13 01:42:44 +0100 | [diff] [blame] | 35 | select SOC_AMD_COMMON_BLOCK_DATA_FABRIC |
Felix Held | 28e2353 | 2021-02-24 20:52:08 +0100 | [diff] [blame] | 36 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
Zheng Bao | 3da5569 | 2021-01-26 18:30:18 +0800 | [diff] [blame] | 37 | select SOC_AMD_COMMON_BLOCK_LPC |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 38 | select SOC_AMD_COMMON_BLOCK_NONCAR |
Raul E Rangel | a6529e7 | 2021-02-09 14:38:36 -0700 | [diff] [blame] | 39 | select SOC_AMD_COMMON_BLOCK_PCI |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 40 | select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
Felix Held | 338d670 | 2021-01-29 23:13:56 +0100 | [diff] [blame] | 41 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
Felix Held | 4be064a | 2020-12-08 17:21:04 +0100 | [diff] [blame] | 42 | select SOC_AMD_COMMON_BLOCK_SMBUS |
Zheng Bao | 02a5ddd | 2020-12-15 22:16:51 +0800 | [diff] [blame] | 43 | select SOC_AMD_COMMON_BLOCK_SMI |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 44 | select SOC_AMD_COMMON_BLOCK_SMM |
Raul E Rangel | 5461662 | 2021-02-05 17:29:12 -0700 | [diff] [blame] | 45 | select SOC_AMD_COMMON_BLOCK_SPI |
Felix Held | 65783fb | 2020-12-04 17:38:46 +0100 | [diff] [blame] | 46 | select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H |
Felix Held | 8a3d4d5 | 2021-01-13 03:06:21 +0100 | [diff] [blame] | 47 | select SOC_AMD_COMMON_BLOCK_UART |
Raul E Rangel | 35dc4b0 | 2021-02-12 16:04:27 -0700 | [diff] [blame] | 48 | select SOC_AMD_COMMON_BLOCK_UCODE |
Felix Held | cc975c5 | 2021-01-23 00:18:08 +0100 | [diff] [blame] | 49 | select SSE2 |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 50 | select UDK_2017_BINDING |
Felix Held | f09221c | 2021-01-22 23:50:54 +0100 | [diff] [blame] | 51 | select X86_AMD_FIXED_MTRRS |
Felix Held | 7aacdd1 | 2021-02-10 23:27:47 +0100 | [diff] [blame] | 52 | select X86_AMD_INIT_SIPI |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 53 | |
Raul E Rangel | 35dc4b0 | 2021-02-12 16:04:27 -0700 | [diff] [blame] | 54 | config SOC_AMD_COMMON_BLOCK_UCODE_SIZE |
| 55 | default 5568 |
| 56 | |
Furquan Shaikh | 696f4ea | 2021-01-08 11:48:52 -0800 | [diff] [blame] | 57 | config CHIPSET_DEVICETREE |
| 58 | string |
| 59 | default "soc/amd/cezanne/chipset.cb" |
| 60 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 61 | config EARLY_RESERVED_DRAM_BASE |
| 62 | hex |
| 63 | default 0x2000000 |
| 64 | help |
| 65 | This variable defines the base address of the DRAM which is reserved |
| 66 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 67 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 68 | not use it, thus preventing corruption of OS memory in case of S3 |
| 69 | resume. |
| 70 | |
| 71 | config EARLYRAM_BSP_STACK_SIZE |
| 72 | hex |
| 73 | default 0x1000 |
| 74 | |
| 75 | config PSP_APOB_DRAM_ADDRESS |
| 76 | hex |
| 77 | default 0x2001000 |
| 78 | help |
| 79 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 80 | Block. |
| 81 | |
| 82 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 83 | hex |
| 84 | default 0x1600 |
| 85 | help |
| 86 | Increase this value if preram cbmem console is getting truncated |
| 87 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 88 | config C_ENV_BOOTBLOCK_SIZE |
| 89 | hex |
| 90 | default 0x10000 |
| 91 | help |
| 92 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 93 | This variable controls the DRAM allocation size in linker script |
| 94 | for bootblock stage. |
| 95 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 96 | config ROMSTAGE_ADDR |
| 97 | hex |
| 98 | default 0x2040000 |
| 99 | help |
| 100 | Sets the address in DRAM where romstage should be loaded. |
| 101 | |
| 102 | config ROMSTAGE_SIZE |
| 103 | hex |
| 104 | default 0x80000 |
| 105 | help |
| 106 | Sets the size of DRAM allocation for romstage in linker script. |
| 107 | |
| 108 | config FSP_M_ADDR |
| 109 | hex |
| 110 | default 0x20C0000 |
| 111 | help |
| 112 | Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| 113 | performs relocation of FSP-M to this address. |
| 114 | |
| 115 | config FSP_M_SIZE |
| 116 | hex |
| 117 | default 0x80000 |
| 118 | help |
| 119 | Sets the size of DRAM allocation for FSP-M in linker script. |
| 120 | |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 121 | config FSP_TEMP_RAM_SIZE |
| 122 | hex |
| 123 | default 0x40000 |
| 124 | help |
| 125 | The amount of coreboot-allocated heap and stack usage by the FSP. |
| 126 | |
Raul E Rangel | 72616b3 | 2021-02-05 16:48:42 -0700 | [diff] [blame] | 127 | config VERSTAGE_ADDR |
| 128 | hex |
| 129 | depends on VBOOT_SEPARATE_VERSTAGE |
| 130 | default 0x2140000 |
| 131 | help |
| 132 | Sets the address in DRAM where verstage should be loaded if running |
| 133 | as a separate stage on x86. |
| 134 | |
| 135 | config VERSTAGE_SIZE |
| 136 | hex |
| 137 | depends on VBOOT_SEPARATE_VERSTAGE |
| 138 | default 0x80000 |
| 139 | help |
| 140 | Sets the size of DRAM allocation for verstage in linker script if |
| 141 | running as a separate stage on x86. |
| 142 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 143 | config RAMBASE |
| 144 | hex |
| 145 | default 0x10000000 |
| 146 | |
Raul E Rangel | 72616b3 | 2021-02-05 16:48:42 -0700 | [diff] [blame] | 147 | config RO_REGION_ONLY |
| 148 | string |
| 149 | depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A |
| 150 | default "apu/amdfw" |
| 151 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 152 | config CPU_ADDR_BITS |
| 153 | int |
| 154 | default 48 |
| 155 | |
| 156 | config MMCONF_BASE_ADDRESS |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 157 | default 0xF8000000 |
| 158 | |
| 159 | config MMCONF_BUS_NUMBER |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 160 | default 64 |
| 161 | |
Felix Held | 8861562 | 2021-01-19 23:51:45 +0100 | [diff] [blame] | 162 | config MAX_CPUS |
| 163 | int |
| 164 | default 16 |
| 165 | |
Felix Held | 8a3d4d5 | 2021-01-13 03:06:21 +0100 | [diff] [blame] | 166 | config CONSOLE_UART_BASE_ADDRESS |
| 167 | depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART |
| 168 | hex |
| 169 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 170 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| 171 | |
Felix Held | ee2a365 | 2021-02-09 23:43:17 +0100 | [diff] [blame] | 172 | config SMM_TSEG_SIZE |
| 173 | hex |
Felix Held | e22eef7 | 2021-02-10 22:22:07 +0100 | [diff] [blame] | 174 | default 0x800000 if HAVE_SMI_HANDLER |
Felix Held | ee2a365 | 2021-02-09 23:43:17 +0100 | [diff] [blame] | 175 | default 0x0 |
| 176 | |
| 177 | config SMM_RESERVED_SIZE |
| 178 | hex |
| 179 | default 0x180000 |
| 180 | |
| 181 | config SMM_MODULE_STACK_SIZE |
| 182 | hex |
| 183 | default 0x800 |
| 184 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 185 | menu "PSP Configuration Options" |
| 186 | |
| 187 | config AMD_FWM_POSITION_INDEX |
| 188 | int "Firmware Directory Table location (0 to 5)" |
| 189 | range 0 5 |
| 190 | default 0 if BOARD_ROMSIZE_KB_512 |
| 191 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 192 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 193 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 194 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 195 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 196 | help |
| 197 | Typically this is calculated by the ROM size, but there may |
| 198 | be situations where you want to put the firmware directory |
| 199 | table in a different location. |
| 200 | 0: 512 KB - 0xFFFA0000 |
| 201 | 1: 1 MB - 0xFFF20000 |
| 202 | 2: 2 MB - 0xFFE20000 |
| 203 | 3: 4 MB - 0xFFC20000 |
| 204 | 4: 8 MB - 0xFF820000 |
| 205 | 5: 16 MB - 0xFF020000 |
| 206 | |
| 207 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 208 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 209 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 210 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 211 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 212 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 213 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 214 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 215 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 216 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 217 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 218 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 219 | |
| 220 | config AMDFW_CONFIG_FILE |
| 221 | string |
| 222 | default "src/soc/amd/cezanne/fw.cfg" |
| 223 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 224 | config PSP_LOAD_MP2_FW |
| 225 | bool |
| 226 | default n |
| 227 | help |
| 228 | Include the MP2 firmwares and configuration into the PSP build. |
| 229 | |
| 230 | If unsure, answer 'n' |
| 231 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 232 | config PSP_UNLOCK_SECURE_DEBUG |
| 233 | bool "Unlock secure debug" |
| 234 | default y |
| 235 | help |
| 236 | Select this item to enable secure debug options in PSP. |
| 237 | |
| 238 | endmenu |
| 239 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 240 | endif # SOC_AMD_CEZANNE |