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huang lin82ba4d02014-08-16 10:49:32 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2014 Rockchip Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
huang lin82ba4d02014-08-16 10:49:32 +080014 */
15
16#ifndef __SOC_ROCKCHIP_RK3288_CHIP_H__
17#define __SOC_ROCKCHIP_RK3288_CHIP_H__
18
huang lin40f558e2014-09-19 14:51:52 +080019#include <soc/gpio.h>
David Hendricksaf42f062015-06-17 13:47:28 -070020#include <soc/vop.h> /* for vop_modes enum used in devicetree.cb */
huang lin40f558e2014-09-19 14:51:52 +080021
huang lin82ba4d02014-08-16 10:49:32 +080022struct soc_rockchip_rk3288_config {
huang lin40f558e2014-09-19 14:51:52 +080023 u32 vop_id;
24 gpio_t lcd_bl_pwm_gpio;
25 gpio_t lcd_bl_en_gpio;
huang lin40f558e2014-09-19 14:51:52 +080026 u32 bl_power_on_udelay;
27 u32 bl_pwm_to_enable_udelay;
28 u32 framebuffer_bits_per_pixel;
Yakir Yang68f42be2015-04-29 10:08:12 -050029 u32 vop_mode;
huang lin82ba4d02014-08-16 10:49:32 +080030};
31
32#endif /* __SOC_ROCKCHIP_RK3288_CHIP_H__ */