rockchip: support display
Implement VOP and eDP drivers, vop and edp clock configuration,
framebuffer allocation and display configuration logic.
The eDP driver reads panel EDID to determine panel dimensions
and the pixel clock used by the VOP.
The pixel clock is generating using the NPLL.
BUG=chrome-os-partner:31897
TEST=Booted Veyron Pinky and display normal
BRANCH=None
Change-Id: I01b5c347a3433a108806aec61aa3a875cab8c129
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e4f863b0b57f2f5293ea8015db86cf7f8acc5853
Original-Change-Id: I61214f55e96bc1dcda9b0f700e5db11e49e5e533
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219050
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9553
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/soc/rockchip/rk3288/chip.h b/src/soc/rockchip/rk3288/chip.h
index a7fded0..b401ab4 100644
--- a/src/soc/rockchip/rk3288/chip.h
+++ b/src/soc/rockchip/rk3288/chip.h
@@ -20,28 +20,16 @@
#ifndef __SOC_ROCKCHIP_RK3288_CHIP_H__
#define __SOC_ROCKCHIP_RK3288_CHIP_H__
+#include <soc/gpio.h>
+
struct soc_rockchip_rk3288_config {
- int screen_type;
- int lvds_format;
- int out_face;
- int clock_frequency;
- int hactive;
- int vactive;
- int hback_porch;
- int hfront_porch;
- int vback_porch;
- int vfront_porch;
- int hsync_len;
- int vsync_len;
- int hsync_active;
- int vsync_active;
- int de_active;
- int pixelclk_active;
- int swap_rb;
- int swap_rg;
- int swap_gb;
- int lcd_en_gpio;
- int lcd_cs_gpio;
+ u32 vop_id;
+ gpio_t lcd_bl_pwm_gpio;
+ gpio_t lcd_bl_en_gpio;
+ u32 lcd_power_on_udelay;
+ u32 bl_power_on_udelay;
+ u32 bl_pwm_to_enable_udelay;
+ u32 framebuffer_bits_per_pixel;
};
#endif /* __SOC_ROCKCHIP_RK3288_CHIP_H__ */