Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com> |
| 5 | * |
| 6 | * This program is free software: you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation, either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | /** |
| 18 | * @file post_codes.h |
Martin Roth | 2507820 | 2015-01-06 21:05:23 -0700 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | /* |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 22 | * This aims to be a central point for POST codes used throughout coreboot. |
| 23 | * All POST codes should be declared here as macros, and post_code() should |
| 24 | * be used with the macros instead of hardcoded values. This allows us to |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 25 | * quickly reference POST codes when nothing is working |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 26 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 27 | * The format for a POST code macro is |
| 28 | * #define POST_WHAT_WE_COMMUNICATE_IS_HAPPENING_WHEN_THIS_CODE_IS_POSTED |
| 29 | * Lets's keep it at POST_* instead of POST_CODE_* |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 30 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 31 | * This file is also included by early assembly files. Only use #define s; |
| 32 | * no function prototypes allowed here |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 33 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 34 | * DOCUMENTATION: |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 35 | * Please document any and all post codes using Doxygen style comments. We |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 36 | * want to be able to generate a verbose enough documentation that is useful |
| 37 | * during debugging. Failure to do so will result in your patch being rejected |
| 38 | * without any explanation or effort on part of the maintainers. |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 39 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 40 | */ |
Martin Roth | 2507820 | 2015-01-06 21:05:23 -0700 | [diff] [blame] | 41 | |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 42 | #ifndef POST_CODES_H |
| 43 | #define POST_CODES_H |
| 44 | |
| 45 | /** |
| 46 | * \brief Entry into 'crt0.s'. reset code jumps to here |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 47 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 48 | * First instruction that gets executed after the reset vector jumps. |
| 49 | * This indicates that the reset vector points to the correct code segment. |
| 50 | */ |
| 51 | #define POST_RESET_VECTOR_CORRECT 0x01 |
| 52 | |
| 53 | /** |
| 54 | * \brief Entry into protected mode |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 55 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 56 | * Preparing to enter protected mode. This is POSTed right before changing to |
| 57 | * protected mode. |
| 58 | */ |
| 59 | #define POST_ENTER_PROTECTED_MODE 0x10 |
| 60 | |
| 61 | /** |
| 62 | * \brief Start copying coreboot to RAM with decompression if compressed |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 63 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 64 | * POSTed before ramstage is about to be loaded into memory |
| 65 | */ |
| 66 | #define POST_PREPARE_RAMSTAGE 0x11 |
| 67 | |
| 68 | /** |
| 69 | * \brief Copy/decompression finished; jumping to RAM |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 70 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 71 | * This is called after ramstage is loaded in memory, and before |
| 72 | * the code jumps there. This represents the end of romstage. |
| 73 | */ |
| 74 | #define POST_RAMSTAGE_IS_PREPARED 0x12 |
| 75 | |
| 76 | |
| 77 | /** |
| 78 | * \brief Entry into c_start |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 79 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 80 | * c_start.S is the first code executing in ramstage. |
| 81 | */ |
| 82 | #define POST_ENTRY_C_START 0x13 |
| 83 | |
| 84 | /** |
Stefan Reinauer | 6adef08 | 2013-05-09 16:30:06 -0700 | [diff] [blame] | 85 | * \brief Pre call to ram stage main() |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 86 | * |
Stefan Reinauer | 6adef08 | 2013-05-09 16:30:06 -0700 | [diff] [blame] | 87 | * POSTed right before ram stage main() is called from c_start.S |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 88 | */ |
| 89 | #define POST_PRE_HARDWAREMAIN 0x79 |
| 90 | |
| 91 | /** |
Stefan Reinauer | 6adef08 | 2013-05-09 16:30:06 -0700 | [diff] [blame] | 92 | * \brief Entry into coreboot in ram stage main() |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 93 | * |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 94 | * This is the first call in hardwaremain.c. If this code is POSTed, then |
| 95 | * ramstage has successfully loaded and started executing. |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 96 | */ |
| 97 | #define POST_ENTRY_RAMSTAGE 0x80 |
| 98 | |
| 99 | /** |
| 100 | * \brief Console is initialized |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 101 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 102 | * The console is initialized and is ready for usage |
| 103 | */ |
| 104 | #define POST_CONSOLE_READY 0x39 |
| 105 | |
| 106 | /** |
| 107 | * \brief Console boot message succeeded |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 108 | * |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 109 | * First console message has been successfully sent through the console backend |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 110 | * driver. |
| 111 | */ |
| 112 | #define POST_CONSOLE_BOOT_MSG 0x40 |
| 113 | |
| 114 | /** |
Vikram Narayanan | 0713ca3 | 2012-01-23 01:44:44 +0530 | [diff] [blame] | 115 | * \brief Before enabling the cache |
| 116 | * |
| 117 | * Going to enable the cache |
| 118 | */ |
| 119 | #define POST_ENABLING_CACHE 0x60 |
| 120 | |
| 121 | /** |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 122 | * \brief Before Device Probe |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 123 | * |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 124 | * Boot State Machine: bs_pre_device() |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 125 | */ |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 126 | #define POST_BS_PRE_DEVICE 0x70 |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 127 | |
| 128 | /** |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 129 | * \brief Initializing Chips |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 130 | * |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 131 | * Boot State Machine: bs_dev_init_chips() |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 132 | */ |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 133 | #define POST_BS_DEV_INIT_CHIPS 0x71 |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 134 | |
| 135 | /** |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 136 | * \brief Starting Device Enumeration |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 137 | * |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 138 | * Boot State Machine: bs_dev_enumerate() |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 139 | */ |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 140 | #define POST_BS_DEV_ENUMERATE 0x72 |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 141 | |
| 142 | /** |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 143 | * \brief Device Resource Allocatio |
Stefan Reinauer | 52095f5 | 2012-08-07 13:14:20 -0700 | [diff] [blame] | 144 | * |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 145 | * Boot State Machine: bs_dev_resources() |
Stefan Reinauer | 52095f5 | 2012-08-07 13:14:20 -0700 | [diff] [blame] | 146 | */ |
Duncan Laurie | cb73a84 | 2013-06-10 10:41:04 -0700 | [diff] [blame] | 147 | #define POST_BS_DEV_RESOURCES 0x73 |
| 148 | |
| 149 | /** |
| 150 | * \brief Device Enable |
| 151 | * |
| 152 | * Boot State Machine: bs_dev_enable() |
| 153 | */ |
| 154 | #define POST_BS_DEV_ENABLE 0x74 |
| 155 | |
| 156 | /** |
| 157 | * \brief Device Initialization |
| 158 | * |
| 159 | * Boot State Machine: bs_dev_init() |
| 160 | */ |
| 161 | #define POST_BS_DEV_INIT 0x75 |
| 162 | |
| 163 | /** |
| 164 | * \brief After Device Probe |
| 165 | * |
| 166 | * Boot State Machine: bs_post_device() |
| 167 | */ |
| 168 | #define POST_BS_POST_DEVICE 0x76 |
| 169 | |
| 170 | /** |
| 171 | * \brief OS Resume Check |
| 172 | * |
| 173 | * Boot State Machine: bs_os_resume_check() |
| 174 | */ |
| 175 | #define POST_BS_OS_RESUME_CHECK 0x77 |
| 176 | |
| 177 | /** |
| 178 | * \brief OS Resume |
| 179 | * |
| 180 | * Boot State Machine: bs_os_resume() |
| 181 | */ |
| 182 | #define POST_BS_OS_RESUME 0x78 |
| 183 | |
| 184 | /** |
| 185 | * \brief Write Tables |
| 186 | * |
| 187 | * Boot State Machine: bs_write_tables() |
| 188 | */ |
| 189 | #define POST_BS_WRITE_TABLES 0x79 |
| 190 | |
| 191 | /** |
| 192 | * \brief Load Payload |
| 193 | * |
| 194 | * Boot State Machine: bs_payload_load() |
| 195 | */ |
| 196 | #define POST_BS_PAYLOAD_LOAD 0x7a |
| 197 | |
| 198 | /** |
| 199 | * \brief Boot Payload |
| 200 | * |
| 201 | * Boot State Machine: bs_payload_boot() |
| 202 | */ |
| 203 | #define POST_BS_PAYLOAD_BOOT 0x7b |
Stefan Reinauer | 52095f5 | 2012-08-07 13:14:20 -0700 | [diff] [blame] | 204 | |
| 205 | /** |
Duncan Laurie | fb50983 | 2015-11-22 14:53:57 -0800 | [diff] [blame] | 206 | * \brief Before calling FSP TempRamInit |
| 207 | * |
| 208 | * Going to call into FSP binary for TempRamInit phase |
| 209 | */ |
| 210 | #define POST_FSP_TEMP_RAM_INIT 0x90 |
| 211 | |
| 212 | /** |
| 213 | * \brief Before calling FSP TempRamExit |
| 214 | * |
| 215 | * Going to call into FSP binary for TempRamExit phase |
| 216 | */ |
| 217 | #define POST_FSP_TEMP_RAM_EXIT 0x91 |
| 218 | |
| 219 | /** |
| 220 | * \brief Before calling FSP MemoryInit |
| 221 | * |
| 222 | * Going to call into FSP binary for MemoryInit phase |
| 223 | */ |
| 224 | #define POST_FSP_MEMORY_INIT 0x92 |
| 225 | |
| 226 | /** |
| 227 | * \brief Before calling FSP SiliconInit |
| 228 | * |
| 229 | * Going to call into FSP binary for SiliconInit phase |
| 230 | */ |
| 231 | #define POST_FSP_SILICON_INIT 0x93 |
| 232 | |
| 233 | /** |
| 234 | * \brief Before calling FSP Notify before resource allocation |
| 235 | * |
| 236 | * Going to call into FSP binary for Notify phase |
| 237 | */ |
| 238 | #define POST_FSP_NOTIFY_BEFORE_ENUMERATE 0x94 |
| 239 | |
| 240 | /** |
| 241 | * \brief Before calling FSP Notify before finalize |
| 242 | * |
| 243 | * Going to call into FSP binary for Notify phase |
| 244 | */ |
| 245 | #define POST_FSP_NOTIFY_BEFORE_FINALIZE 0x95 |
| 246 | |
| 247 | /** |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 248 | * \brief Entry into elf boot |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 249 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 250 | * This POST code is called right before invoking jmp_to_elf_entry() |
| 251 | * jmp_to_elf_entry() invokes the payload, and should never return |
| 252 | */ |
| 253 | #define POST_ENTER_ELF_BOOT 0xf8 |
| 254 | |
| 255 | /** |
| 256 | * \brief Jumping to payload |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 257 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 258 | * Called right before jumping to a payload. If the boot sequence stops with |
| 259 | * this code, chances are the payload freezes. |
| 260 | */ |
| 261 | #define POST_JUMPING_TO_PAYLOAD 0xf3 |
| 262 | |
| 263 | /** |
Duncan Laurie | 4397aa1 | 2014-05-12 10:22:01 -0700 | [diff] [blame] | 264 | * \brief TPM failure |
| 265 | * |
| 266 | * An error with the TPM, either unexepcted state or communications failure. |
| 267 | */ |
| 268 | #define POST_TPM_FAILURE 0xed |
| 269 | |
| 270 | /** |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 271 | * \brief Not supposed to get here |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 272 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 273 | * A function that should not have returned, returned |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 274 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 275 | * Check the console output for details. |
| 276 | */ |
| 277 | #define POST_DEAD_CODE 0xee |
| 278 | |
| 279 | /** |
Duncan Laurie | 727b545 | 2013-08-08 16:28:41 -0700 | [diff] [blame] | 280 | * \brief Resume from suspend failed |
| 281 | * |
| 282 | * This post code is sent when the firmware is expected to resume it is |
| 283 | * unable to do so. |
| 284 | */ |
| 285 | #define POST_RESUME_FAILURE 0xef |
| 286 | |
| 287 | /** |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 288 | * \brief Final code before OS resumes |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 289 | * |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 290 | * Called right before jumping to the OS resume vector. |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 291 | */ |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 292 | #define POST_OS_RESUME 0xfd |
| 293 | |
| 294 | /** |
| 295 | * \brief Final code before OS boots |
| 296 | * |
| 297 | * This may not be called depending on the payload used. |
| 298 | */ |
| 299 | #define POST_OS_BOOT 0xfe |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 300 | |
| 301 | /** |
| 302 | * \brief Elfload fail or die() called |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 303 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 304 | * Coreboot was not able to load the payload, no payload was detected |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 305 | * or die() was called. |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 306 | * \n |
| 307 | * If this code appears before entering ramstage, then most likely |
| 308 | * ramstage is corrupted, and reflashing of the ROM chip is needed. |
| 309 | * \n |
| 310 | * If this code appears after ramstage, there is a problem with the payload |
| 311 | * If the payload was built out-of-tree, check that it was compiled as |
| 312 | * a coreboot payload |
| 313 | * \n |
| 314 | * Check the console output to see exactly where the failure occured. |
| 315 | */ |
| 316 | #define POST_DIE 0xff |
| 317 | |
| 318 | |
| 319 | /* |
| 320 | * The following POST codes are taken from src/include/cpu/amd/geode_post_code.h |
| 321 | * They overlap with previous codes, and most are not even used |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 322 | * Some mainboards still require them, but they are deprecated. We want to consolidate |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 323 | * our own POST code structure with the codes above. |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 324 | * |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 325 | * standard AMD post definitions for the AMD Geode |
| 326 | */ |
| 327 | #define POST_Output_Port (0x080) /* port to write post codes to*/ |
| 328 | |
| 329 | #define POST_preSioInit (0x000) |
| 330 | #define POST_clockInit (0x001) |
| 331 | #define POST_CPURegInit (0x002) |
| 332 | #define POST_UNREAL (0x003) |
| 333 | #define POST_CPUMemRegInit (0x004) |
| 334 | #define POST_CPUTest (0x005) |
| 335 | #define POST_memSetup (0x006) |
| 336 | #define POST_memSetUpStack (0x007) |
| 337 | #define POST_memTest (0x008) |
| 338 | #define POST_shadowRom (0x009) |
| 339 | #define POST_memRAMoptimize (0x00A) |
| 340 | #define POST_cacheInit (0x00B) |
| 341 | #define POST_northBridgeInit (0x00C) |
| 342 | #define POST_chipsetInit (0x00D) |
| 343 | #define POST_sioTest (0x00E) |
| 344 | #define POST_pcATjunk (0x00F) |
| 345 | |
| 346 | #define POST_intTable (0x010) |
| 347 | #define POST_memInfo (0x011) |
| 348 | #define POST_romCopy (0x012) |
| 349 | #define POST_PLLCheck (0x013) |
| 350 | #define POST_keyboardInit (0x014) |
| 351 | #define POST_cpuCacheOff (0x015) |
| 352 | #define POST_BDAInit (0x016) |
| 353 | #define POST_pciScan (0x017) |
| 354 | #define POST_optionRomInit (0x018) |
| 355 | #define POST_ResetLimits (0x019) |
| 356 | #define POST_summary_screen (0x01A) |
| 357 | #define POST_Boot (0x01B) |
| 358 | #define POST_SystemPreInit (0x01C) |
| 359 | #define POST_ClearRebootFlag (0x01D) |
| 360 | #define POST_GLIUInit (0x01E) |
| 361 | #define POST_BootFailed (0x01F) |
| 362 | |
| 363 | #define POST_CPU_ID (0x020) |
| 364 | #define POST_COUNTERBROKEN (0x021) |
| 365 | #define POST_DIFF_DIMMS (0x022) |
| 366 | #define POST_WIGGLE_MEM_LINES (0x023) |
| 367 | #define POST_NO_GLIU_DESC (0x024) |
| 368 | #define POST_CPU_LCD_CHECK (0x025) |
| 369 | #define POST_CPU_LCD_PASS (0x026) |
| 370 | #define POST_CPU_LCD_FAIL (0x027) |
| 371 | #define POST_CPU_STEPPING (0x028) |
| 372 | #define POST_CPU_DM_BIST_FAILURE (0x029) |
| 373 | #define POST_CPU_FLAGS (0x02A) |
| 374 | #define POST_CHIPSET_ID (0x02B) |
| 375 | #define POST_CHIPSET_ID_PASS (0x02C) |
| 376 | #define POST_CHIPSET_ID_FAIL (0x02D) |
| 377 | #define POST_CPU_ID_GOOD (0x02E) |
| 378 | #define POST_CPU_ID_FAIL (0x02F) |
| 379 | |
| 380 | /* PCI config*/ |
| 381 | #define P80_PCICFG (0x030) |
| 382 | |
| 383 | /* PCI io*/ |
| 384 | #define P80_PCIIO (0x040) |
| 385 | |
| 386 | /* PCI memory*/ |
| 387 | #define P80_PCIMEM (0x050) |
| 388 | |
| 389 | /* SIO*/ |
| 390 | #define P80_SIO (0x060) |
| 391 | |
| 392 | /* Memory Setp*/ |
| 393 | #define P80_MEM_SETUP (0x070) |
| 394 | #define POST_MEM_SETUP (0x070) |
| 395 | #define ERROR_32BIT_DIMMS (0x071) |
| 396 | #define POST_MEM_SETUP2 (0x072) |
| 397 | #define POST_MEM_SETUP3 (0x073) |
| 398 | #define POST_MEM_SETUP4 (0x074) |
| 399 | #define POST_MEM_SETUP5 (0x075) |
| 400 | #define POST_MEM_ENABLE (0x076) |
| 401 | #define ERROR_NO_DIMMS (0x077) |
| 402 | #define ERROR_DIFF_DIMMS (0x078) |
| 403 | #define ERROR_BAD_LATENCY (0x079) |
| 404 | #define ERROR_SET_PAGE (0x07A) |
| 405 | #define ERROR_DENSITY_DIMM (0x07B) |
| 406 | #define ERROR_UNSUPPORTED_DIMM (0x07C) |
| 407 | #define ERROR_BANK_SET (0x07D) |
| 408 | #define POST_MEM_SETUP_GOOD (0x07E) |
| 409 | #define POST_MEM_SETUP_FAIL (0x07F) |
| 410 | |
| 411 | #define POST_UserPreInit (0x080) |
| 412 | #define POST_UserPostInit (0x081) |
| 413 | #define POST_Equipment_check (0x082) |
| 414 | #define POST_InitNVRAMBX (0x083) |
| 415 | #define POST_NoPIRTable (0x084) |
| 416 | #define POST_ChipsetFingerPrintPass (0x085) |
| 417 | #define POST_ChipsetFingerPrintFail (0x086) |
| 418 | #define POST_CPU_IM_TAG_BIST_FAILURE (0x087) |
| 419 | #define POST_CPU_IM_DATA_BIST_FAILURE (0x088) |
| 420 | #define POST_CPU_FPU_BIST_FAILURE (0x089) |
| 421 | #define POST_CPU_BTB_BIST_FAILURE (0x08A) |
| 422 | #define POST_CPU_EX_BIST_FAILURE (0x08B) |
| 423 | #define POST_Chipset_PI_Test_Fail (0x08C) |
| 424 | #define POST_Chipset_SMBus_SDA_Test_Fail (0x08D) |
| 425 | #define POST_BIT_CLK_Fail (0x08E) |
| 426 | |
| 427 | #define POST_STACK_SETUP (0x090) |
| 428 | #define POST_CPU_PF_BIST_FAILURE (0x091) |
| 429 | #define POST_CPU_L2_BIST_FAILURE (0x092) |
| 430 | #define POST_CPU_GLCP_BIST_FAILURE (0x093) |
| 431 | #define POST_CPU_DF_BIST_FAILURE (0x094) |
| 432 | #define POST_CPU_VG_BIST_FAILURE (0x095) |
| 433 | #define POST_CPU_VIP_BIST_FAILURE (0x096) |
| 434 | #define POST_STACK_SETUP_PASS (0x09E) |
| 435 | #define POST_STACK_SETUP_FAIL (0x09F) |
| 436 | |
| 437 | #define POST_PLL_INIT (0x0A0) |
| 438 | #define POST_PLL_MANUAL (0x0A1) |
| 439 | #define POST_PLL_STRAP (0x0A2) |
| 440 | #define POST_PLL_RESET_FAIL (0x0A3) |
| 441 | #define POST_PLL_PCI_FAIL (0x0A4) |
| 442 | #define POST_PLL_MEM_FAIL (0x0A5) |
| 443 | #define POST_PLL_CPU_VER_FAIL (0x0A6) |
| 444 | |
| 445 | #define POST_MEM_TESTMEM (0x0B0) |
| 446 | #define POST_MEM_TESTMEM1 (0x0B1) |
| 447 | #define POST_MEM_TESTMEM2 (0x0B2) |
| 448 | #define POST_MEM_TESTMEM3 (0x0B3) |
| 449 | #define POST_MEM_TESTMEM4 (0x0B4) |
| 450 | #define POST_MEM_TESTMEM_PASS (0x0BE) |
| 451 | #define POST_MEM_TESTMEM_FAIL (0x0BF) |
| 452 | |
| 453 | #define POST_SECUROM_SECBOOT_START (0x0C0) |
| 454 | #define POST_SECUROM_BOOTSRCSETUP (0x0C1) |
| 455 | #define POST_SECUROM_REMAP_FAIL (0x0C2) |
| 456 | #define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) |
| 457 | #define POST_SECUROM_DCACHESETUP (0x0C4) |
| 458 | #define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) |
| 459 | #define POST_SECUROM_ICACHESETUP (0x0C6) |
| 460 | #define POST_SECUROM_DESCRIPTORSETUP (0x0C7) |
| 461 | #define POST_SECUROM_DCACHESETUPBIOS (0x0C8) |
| 462 | #define POST_SECUROM_PLATFORMSETUP (0x0C9) |
| 463 | #define POST_SECUROM_SIGCHECKBIOS (0x0CA) |
| 464 | #define POST_SECUROM_ICACHESETUPBIOS (0x0CB) |
| 465 | #define POST_SECUROM_PASS (0x0CC) |
| 466 | #define POST_SECUROM_FAIL (0x0CD) |
| 467 | |
| 468 | #define POST_RCONFInitError (0x0CE) |
| 469 | #define POST_CacheInitError (0x0CF) |
| 470 | |
| 471 | #define POST_ROM_PREUNCOMPRESS (0x0D0) |
| 472 | #define POST_ROM_UNCOMPRESS (0x0D1) |
| 473 | #define POST_ROM_SMM_INIT (0x0D2) |
| 474 | #define POST_ROM_VID_BIOS (0x0D3) |
| 475 | #define POST_ROM_LCDINIT (0x0D4) |
| 476 | #define POST_ROM_SPLASH (0x0D5) |
| 477 | #define POST_ROM_HDDINIT (0x0D6) |
| 478 | #define POST_ROM_SYS_INIT (0x0D7) |
| 479 | #define POST_ROM_DMM_INIT (0x0D8) |
| 480 | #define POST_ROM_TVINIT (0x0D9) |
| 481 | #define POST_ROM_POSTUNCOMPRESS (0x0DE) |
| 482 | |
| 483 | #define P80_CHIPSET_INIT (0x0E0) |
| 484 | #define POST_PreChipsetInit (0x0E1) |
| 485 | #define POST_LateChipsetInit (0x0E2) |
| 486 | #define POST_NORTHB_INIT (0x0E8) |
| 487 | |
| 488 | #define POST_INTR_SEG_JUMP (0x0F0) |
| 489 | |
| 490 | #endif /* THE_ALMIGHTY_POST_CODES_H */ |