Blame - src/cpu/x86/lapic/secondary.S - coreboot

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Eric Biederman	fcd5ace	2004-10-14 19:29:29 +0000	[diff] [blame]	1	#include <cpu/x86/mtrr.h>
				2	#include <cpu/x86/lapic_def.h>
Stefan Reinauer	5f5436f	2010-04-25 20:42:02 +0000	[diff] [blame]	3
Stefan Reinauer	82ecf4c	2012-11-15 15:53:30 -0800	[diff] [blame]	4	#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
Eric Biederman	fcd5ace	2004-10-14 19:29:29 +0000	[diff] [blame]	5	.text
Aaron Durbin	a146d58	2013-02-08 16:56:51 -0600	[diff] [blame]	6	.globl _secondary_start, _secondary_start_end, _secondary_gdt_addr
Sven Schnelle	51676b1	2012-07-29 19:18:03 +0200	[diff] [blame]	7	.balign 4096
Eric Biederman	fcd5ace	2004-10-14 19:29:29 +0000	[diff] [blame]	8	_secondary_start:
				9	.code16
				10	cli
				11	xorl %eax, %eax
				12	movl %eax, %cr3 /* Invalidate TLB*/
				13
				14	/* On hyper threaded cpus, invalidating the cache here is
				15	* very very bad. Don't.
				16	*/
				17
				18	/* setup the data segment */
				19	movw %cs, %ax
				20	movw %ax, %ds
				21
				22	data32 lgdt gdtaddr - _secondary_start
				23
				24	movl %cr0, %eax
				25	andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
				26	orl $0x60000001, %eax /* CD, NW, PE = 1 */
				27	movl %eax, %cr0
				28
Kyösti Mälkki	63539bb	2012-07-05 06:31:15 +0300	[diff] [blame]	29	ljmpl $0x10, $__ap_protected_start
				30
Aaron Durbin	a146d58	2013-02-08 16:56:51 -0600	[diff] [blame]	31	/* This will get filled in by C code. */
				32	_secondary_gdt_addr:
Kyösti Mälkki	63539bb	2012-07-05 06:31:15 +0300	[diff] [blame]	33	gdtaddr:
Aaron Durbin	a146d58	2013-02-08 16:56:51 -0600	[diff] [blame]	34	.word 0 /* the table limit */
				35	.long 0 /* we know the offset */
Kyösti Mälkki	63539bb	2012-07-05 06:31:15 +0300	[diff] [blame]	36
				37	_secondary_start_end:
				38
				39	ap_protected_start:
Eric Biederman	fcd5ace	2004-10-14 19:29:29 +0000	[diff] [blame]	40	.code32
Kyösti Mälkki	63539bb	2012-07-05 06:31:15 +0300	[diff] [blame]	41	lgdt gdtaddr
				42	ljmpl $0x10, $__ap_protected_start
				43
				44	__ap_protected_start:
				45
Eric Biederman	fcd5ace	2004-10-14 19:29:29 +0000	[diff] [blame]	46	movw $0x18, %ax
				47	movw %ax, %ds
				48	movw %ax, %es
				49	movw %ax, %ss
				50	movw %ax, %fs
				51	movw %ax, %gs
				52
Eric Biederman	f8a2ddd	2004-10-30 08:05:41 +0000	[diff] [blame]	53	/* Load the Interrupt descriptor table */
				54	lidt idtarg
				55
Sven Schnelle	51676b1	2012-07-29 19:18:03 +0200	[diff] [blame]	56	/* Set the stack pointer, and flag that we are done */
				57	xorl %eax, %eax
				58	movl secondary_stack, %esp
Ronald G. Minnich	8b93059	2012-06-05 14:41:27 -0700	[diff] [blame]	59	movl secondary_cpu_index, %edi
				60	pushl %edi
Sven Schnelle	51676b1	2012-07-29 19:18:03 +0200	[diff] [blame]	61	movl %eax, secondary_stack
Eric Biederman	fcd5ace	2004-10-14 19:29:29 +0000	[diff] [blame]	62
				63	call secondary_cpu_init
				64	1: hlt
				65	jmp 1b
				66
Eric Biederman	fcd5ace	2004-10-14 19:29:29 +0000	[diff] [blame]	67	.code32
Stefan Reinauer	82ecf4c	2012-11-15 15:53:30 -0800	[diff] [blame]	68	#endif