Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 5 | * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 6 | * Copyright (C) 2007-2008 coresystems GmbH |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 7 | * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com> |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 17 | */ |
| 18 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 19 | #include <cpu/x86/mtrr.h> |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 20 | #include <cpu/x86/cache.h> |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 21 | #include <cpu/x86/post_code.h> |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 22 | #include <cpu/x86/lapic_def.h> |
| 23 | |
| 24 | /* Macro to access Local APIC registers at default base. */ |
| 25 | #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 26 | #define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 27 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 28 | #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE |
| 29 | #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |
| 30 | |
| 31 | /* Save the BIST result. */ |
| 32 | movl %eax, %ebp |
| 33 | |
| 34 | cache_as_ram: |
| 35 | post_code(0x20) |
| 36 | |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 37 | movl $LAPIC_BASE_MSR, %ecx |
| 38 | rdmsr |
| 39 | andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax |
| 40 | jz ap_init |
| 41 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 42 | /* Zero out all fixed range and variable range MTRRs. |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 43 | * For hyper-threaded CPUs these are shared. |
| 44 | */ |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 45 | movl $mtrr_table, %esi |
Stefan Reinauer | 4a45ec4 | 2015-07-07 00:54:05 +0200 | [diff] [blame] | 46 | movl $((mtrr_table_end - mtrr_table) >> 1), %edi |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 47 | xorl %eax, %eax |
| 48 | xorl %edx, %edx |
| 49 | clear_mtrrs: |
| 50 | movw (%esi), %bx |
| 51 | movzx %bx, %ecx |
| 52 | wrmsr |
| 53 | add $2, %esi |
| 54 | dec %edi |
| 55 | jnz clear_mtrrs |
| 56 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 57 | post_code(0x21) |
| 58 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 59 | /* Configure the default memory type to uncacheable. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 60 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 61 | rdmsr |
| 62 | andl $(~0x00000cff), %eax |
| 63 | wrmsr |
| 64 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 65 | post_code(0x22) |
| 66 | |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 67 | /* Determine CPU_ADDR_BITS and load PHYSMASK high |
| 68 | * word to %edx. |
| 69 | */ |
| 70 | movl $0x80000000, %eax |
| 71 | cpuid |
| 72 | cmpl $0x80000008, %eax |
| 73 | jc addrsize_no_MSR |
| 74 | movl $0x80000008, %eax |
| 75 | cpuid |
| 76 | movb %al, %cl |
| 77 | sub $32, %cl |
| 78 | movl $1, %edx |
| 79 | shl %cl, %edx |
| 80 | subl $1, %edx |
| 81 | jmp addrsize_set_high |
| 82 | addrsize_no_MSR: |
| 83 | movl $1, %eax |
| 84 | cpuid |
| 85 | andl $(1<<6 | 1<<17), %edx /* PAE or PSE36 */ |
| 86 | jz addrsize_set_high |
| 87 | movl $0x0f, %edx |
| 88 | |
| 89 | /* Preload high word of address mask (in %edx) for Variable |
| 90 | * MTRRs 0 and 1 and enable local apic at default base. |
| 91 | */ |
| 92 | addrsize_set_high: |
| 93 | xorl %eax, %eax |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 94 | movl $MTRR_PHYS_MASK(0), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 95 | wrmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 96 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 97 | wrmsr |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 98 | movl $LAPIC_BASE_MSR, %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 99 | not %edx |
| 100 | movl %edx, %ebx |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 101 | rdmsr |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 102 | andl %ebx, %edx |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 103 | andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax |
| 104 | orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax |
| 105 | wrmsr |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 106 | |
| 107 | bsp_init: |
| 108 | |
| 109 | post_code(0x23) |
| 110 | |
| 111 | /* Send INIT IPI to all excluding ourself. */ |
| 112 | movl LAPIC(ICR), %edi |
| 113 | movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax |
| 114 | 1: movl %eax, (%edi) |
| 115 | movl $0x30, %ecx |
| 116 | 2: pause |
| 117 | dec %ecx |
| 118 | jnz 2b |
| 119 | movl (%edi), %ecx |
| 120 | andl $LAPIC_ICR_BUSY, %ecx |
| 121 | jnz 1b |
| 122 | |
| 123 | post_code(0x24) |
Patrick Georgi | 819c7d4 | 2012-03-31 13:08:12 +0200 | [diff] [blame] | 124 | |
Kyösti Mälkki | df0fbc7 | 2012-07-04 12:02:58 +0300 | [diff] [blame] | 125 | movl $1, %eax |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 126 | cpuid |
| 127 | btl $28, %edx |
| 128 | jnc sipi_complete |
| 129 | bswapl %ebx |
Kyösti Mälkki | df0fbc7 | 2012-07-04 12:02:58 +0300 | [diff] [blame] | 130 | movzx %bh, %edi |
| 131 | cmpb $1, %bh |
| 132 | jbe sipi_complete /* only one LAPIC ID in package */ |
| 133 | |
| 134 | movl $0, %eax |
| 135 | cpuid |
| 136 | movb $1, %bl |
| 137 | cmpl $4, %eax |
| 138 | jb cores_counted |
| 139 | movl $4, %eax |
| 140 | movl $0, %ecx |
| 141 | cpuid |
| 142 | shr $26, %eax |
| 143 | movb %al, %bl |
| 144 | inc %bl |
| 145 | |
| 146 | cores_counted: |
| 147 | movl %edi, %eax |
| 148 | divb %bl |
| 149 | cmpb $1, %al |
| 150 | jbe sipi_complete /* only LAPIC ID of a core */ |
| 151 | |
| 152 | /* For a hyper-threading processor, cache must not be disabled |
| 153 | * on an AP on the same physical package with the BSP. |
| 154 | */ |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 155 | |
| 156 | hyper_threading_cpu: |
| 157 | |
| 158 | /* delay 10 ms */ |
| 159 | movl $10000, %ecx |
| 160 | 1: inb $0x80, %al |
| 161 | dec %ecx |
| 162 | jnz 1b |
| 163 | |
| 164 | post_code(0x25) |
| 165 | |
| 166 | /* Send Start IPI to all excluding ourself. */ |
| 167 | movl LAPIC(ICR), %edi |
| 168 | movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax |
| 169 | 1: movl %eax, (%edi) |
| 170 | movl $0x30, %ecx |
| 171 | 2: pause |
| 172 | dec %ecx |
| 173 | jnz 2b |
| 174 | movl (%edi), %ecx |
| 175 | andl $LAPIC_ICR_BUSY, %ecx |
| 176 | jnz 1b |
| 177 | |
| 178 | /* delay 250 us */ |
| 179 | movl $250, %ecx |
| 180 | 1: inb $0x80, %al |
| 181 | dec %ecx |
| 182 | jnz 1b |
| 183 | |
| 184 | post_code(0x26) |
| 185 | |
| 186 | /* Wait for sibling CPU to start. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 187 | 1: movl $(MTRR_PHYS_BASE(0)), %ecx |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 188 | rdmsr |
| 189 | andl %eax, %eax |
| 190 | jnz sipi_complete |
| 191 | |
| 192 | movl $0x30, %ecx |
| 193 | 2: pause |
| 194 | dec %ecx |
| 195 | jnz 2b |
| 196 | jmp 1b |
| 197 | |
| 198 | |
| 199 | ap_init: |
| 200 | post_code(0x27) |
| 201 | |
| 202 | /* Do not disable cache (so BSP can enable it). */ |
| 203 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 204 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 205 | movl %eax, %cr0 |
| 206 | |
| 207 | post_code(0x28) |
| 208 | |
| 209 | /* MTRR registers are shared between HT siblings. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 210 | movl $(MTRR_PHYS_BASE(0)), %ecx |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 211 | movl $(1<<12), %eax |
| 212 | xorl %edx, %edx |
| 213 | wrmsr |
| 214 | |
| 215 | post_code(0x29) |
| 216 | |
| 217 | ap_halt: |
| 218 | cli |
| 219 | 1: hlt |
Kyösti Mälkki | df0fbc7 | 2012-07-04 12:02:58 +0300 | [diff] [blame] | 220 | jmp 1b |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 221 | |
| 222 | |
| 223 | |
| 224 | sipi_complete: |
| 225 | |
| 226 | post_code(0x2a) |
| 227 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 228 | /* Set Cache-as-RAM base address. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 229 | movl $(MTRR_PHYS_BASE(0)), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 230 | movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax |
| 231 | xorl %edx, %edx |
| 232 | wrmsr |
| 233 | |
| 234 | /* Set Cache-as-RAM mask. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 235 | movl $(MTRR_PHYS_MASK(0)), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 236 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 237 | movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 238 | wrmsr |
| 239 | |
| 240 | /* Enable MTRR. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 241 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 242 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 243 | orl $MTRR_DEF_TYPE_EN, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 244 | wrmsr |
| 245 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 246 | post_code(0x2b) |
| 247 | |
Kyösti Mälkki | 05d6ffb | 2012-02-16 23:12:04 +0200 | [diff] [blame] | 248 | /* Enable L2 cache Write-Back (WBINVD and FLUSH#). |
| 249 | * |
| 250 | * MSR is set when DisplayFamily_DisplayModel is one of: |
| 251 | * 06_0x, 06_17, 06_1C |
| 252 | * |
| 253 | * Description says this bit enables use of WBINVD and FLUSH#. |
| 254 | * Should this be set only after the system bus and/or memory |
| 255 | * controller can successfully handle write cycles? |
| 256 | */ |
| 257 | |
| 258 | #define EAX_FAMILY(a) (a << 8) /* for family <= 0fH */ |
| 259 | #define EAX_MODEL(a) (((a & 0xf0) << 12) | ((a & 0xf) << 4)) |
| 260 | |
| 261 | movl $1, %eax |
| 262 | cpuid |
| 263 | movl %eax, %ebx |
| 264 | andl $EAX_FAMILY(0x0f), %eax |
| 265 | cmpl $EAX_FAMILY(0x06), %eax |
| 266 | jne no_msr_11e |
| 267 | movl %ebx, %eax |
| 268 | andl $EAX_MODEL(0xff), %eax |
| 269 | cmpl $EAX_MODEL(0x17), %eax |
| 270 | je has_msr_11e |
| 271 | cmpl $EAX_MODEL(0x1c), %eax |
| 272 | je has_msr_11e |
| 273 | andl $EAX_MODEL(0xf0), %eax |
| 274 | cmpl $EAX_MODEL(0x00), %eax |
| 275 | jne no_msr_11e |
| 276 | has_msr_11e: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 277 | movl $0x11e, %ecx |
| 278 | rdmsr |
| 279 | orl $(1 << 8), %eax |
| 280 | wrmsr |
Kyösti Mälkki | 05d6ffb | 2012-02-16 23:12:04 +0200 | [diff] [blame] | 281 | no_msr_11e: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 282 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 283 | post_code(0x2c) |
| 284 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 285 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 286 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 287 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 288 | invd |
| 289 | movl %eax, %cr0 |
| 290 | |
| 291 | /* Clear the cache memory reagion. */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 292 | cld |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 293 | xorl %eax, %eax |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 294 | movl $CACHE_AS_RAM_BASE, %edi |
Stefan Reinauer | 4a45ec4 | 2015-07-07 00:54:05 +0200 | [diff] [blame] | 295 | movl $(CACHE_AS_RAM_SIZE >> 2), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 296 | rep stosl |
| 297 | |
| 298 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 299 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 300 | orl $CR0_CacheDisable, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 301 | movl %eax, %cr0 |
| 302 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 303 | post_code(0x2d) |
| 304 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 305 | #if CONFIG_XIP_ROM_SIZE |
| 306 | /* Enable cache for our code in Flash because we do XIP here */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 307 | movl $MTRR_PHYS_BASE(1), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 308 | xorl %edx, %edx |
| 309 | /* |
| 310 | * IMPORTANT: The following calculation _must_ be done at runtime. See |
| 311 | * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html |
| 312 | */ |
| 313 | movl $copy_and_run, %eax |
| 314 | andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax |
| 315 | orl $MTRR_TYPE_WRBACK, %eax |
| 316 | wrmsr |
| 317 | |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 318 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 319 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 320 | movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 321 | wrmsr |
| 322 | #endif /* CONFIG_XIP_ROM_SIZE */ |
| 323 | |
| 324 | /* Enable cache. */ |
| 325 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 326 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 327 | movl %eax, %cr0 |
| 328 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 329 | post_code(0x2e) |
| 330 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 331 | /* Set up the stack pointer. */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 332 | movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 333 | |
| 334 | /* Restore the BIST result. */ |
| 335 | movl %ebp, %eax |
| 336 | movl %esp, %ebp |
| 337 | pushl %eax |
| 338 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 339 | post_code(0x2f) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 340 | |
| 341 | /* Call romstage.c main function. */ |
| 342 | call main |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 343 | addl $4, %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 344 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 345 | post_code(0x30) |
| 346 | |
| 347 | /* Disable cache. */ |
| 348 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 349 | orl $CR0_CacheDisable, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 350 | movl %eax, %cr0 |
| 351 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 352 | post_code(0x34) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 353 | |
| 354 | /* Disable MTRR. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 355 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 356 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 357 | andl $(~MTRR_DEF_TYPE_EN), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 358 | wrmsr |
| 359 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 360 | post_code(0x35) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 361 | |
| 362 | invd |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 363 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 364 | post_code(0x36) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 365 | |
| 366 | /* Enable cache. */ |
| 367 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 368 | andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 369 | movl %eax, %cr0 |
| 370 | |
Kyösti Mälkki | 0078ceb | 2012-02-28 02:02:27 +0200 | [diff] [blame] | 371 | post_code(0x37) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 372 | |
| 373 | /* Disable cache. */ |
| 374 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 375 | orl $CR0_CacheDisable, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 376 | movl %eax, %cr0 |
| 377 | |
| 378 | post_code(0x38) |
| 379 | |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 380 | /* Enable Write Back and Speculative Reads for low RAM. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 381 | movl $MTRR_PHYS_BASE(0), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 382 | movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax |
| 383 | xorl %edx, %edx |
| 384 | wrmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 385 | movl $MTRR_PHYS_MASK(0), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 386 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 387 | movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 388 | wrmsr |
| 389 | |
Kyösti Mälkki | 107f72e | 2014-01-06 11:06:26 +0200 | [diff] [blame] | 390 | #if CACHE_ROM_SIZE |
Kyösti Mälkki | 325b92f | 2012-02-28 00:24:15 +0200 | [diff] [blame] | 391 | /* Enable caching and Speculative Reads for Flash ROM device. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 392 | movl $MTRR_PHYS_BASE(1), %ecx |
Kyösti Mälkki | 325b92f | 2012-02-28 00:24:15 +0200 | [diff] [blame] | 393 | movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 394 | xorl %edx, %edx |
| 395 | wrmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 396 | movl $MTRR_PHYS_MASK(1), %ecx |
Kyösti Mälkki | a860c68 | 2012-02-28 02:06:45 +0200 | [diff] [blame] | 397 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 398 | movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 399 | wrmsr |
Kyösti Mälkki | 5458b9d | 2012-06-30 11:41:08 +0300 | [diff] [blame] | 400 | #endif |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 401 | |
| 402 | post_code(0x39) |
| 403 | |
| 404 | /* And enable cache again after setting MTRRs. */ |
| 405 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 406 | andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 407 | movl %eax, %cr0 |
| 408 | |
| 409 | post_code(0x3a) |
| 410 | |
| 411 | /* Enable MTRR. */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 412 | movl $MTRR_DEF_TYPE_MSR, %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 413 | rdmsr |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 414 | orl $MTRR_DEF_TYPE_EN, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 415 | wrmsr |
| 416 | |
| 417 | post_code(0x3b) |
| 418 | |
| 419 | /* Invalidate the cache again. */ |
| 420 | invd |
| 421 | |
| 422 | post_code(0x3c) |
| 423 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 424 | __main: |
| 425 | post_code(POST_PREPARE_RAMSTAGE) |
| 426 | cld /* Clear direction flag. */ |
| 427 | |
Kyösti Mälkki | 1729cd8 | 2014-10-16 12:47:25 +0300 | [diff] [blame] | 428 | movl $CONFIG_RAMTOP, %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 429 | movl %esp, %ebp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 430 | call copy_and_run |
| 431 | |
| 432 | .Lhlt: |
| 433 | post_code(POST_DEAD_CODE) |
| 434 | hlt |
| 435 | jmp .Lhlt |
| 436 | |
| 437 | mtrr_table: |
| 438 | /* Fixed MTRRs */ |
| 439 | .word 0x250, 0x258, 0x259 |
| 440 | .word 0x268, 0x269, 0x26A |
| 441 | .word 0x26B, 0x26C, 0x26D |
| 442 | .word 0x26E, 0x26F |
| 443 | /* Variable MTRRs */ |
| 444 | .word 0x200, 0x201, 0x202, 0x203 |
| 445 | .word 0x204, 0x205, 0x206, 0x207 |
| 446 | .word 0x208, 0x209, 0x20A, 0x20B |
| 447 | .word 0x20C, 0x20D, 0x20E, 0x20F |
| 448 | mtrr_table_end: |