Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
| 5 | * Copyright (C) 2007-2008 coresystems GmbH |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <cpu/x86/stack.h> |
| 22 | #include <cpu/x86/mtrr.h> |
| 23 | #include <cpu/x86/post_code.h> |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 24 | #include <cpu/x86/lapic_def.h> |
| 25 | |
| 26 | /* Macro to access Local APIC registers at default base. */ |
| 27 | #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 28 | |
| 29 | #define CPU_MAXPHYADDR 36 |
| 30 | #define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) |
| 31 | |
Kyösti Mälkki | 325b92f | 2012-02-28 00:24:15 +0200 | [diff] [blame] | 32 | /* Base address to cache all of Flash ROM, just below 4GB. */ |
| 33 | #define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10) |
| 34 | |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 35 | #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE |
| 36 | #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |
| 37 | |
| 38 | /* Save the BIST result. */ |
| 39 | movl %eax, %ebp |
| 40 | |
| 41 | cache_as_ram: |
| 42 | post_code(0x20) |
| 43 | |
| 44 | /* Send INIT IPI to all excluding ourself. */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 45 | movl LAPIC(ICR), %edi |
| 46 | movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax |
| 47 | movl %eax, (%edi) |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 48 | |
| 49 | /* Zero out all fixed range and variable range MTRRs. */ |
| 50 | movl $mtrr_table, %esi |
| 51 | movl $((mtrr_table_end - mtrr_table) / 2), %edi |
| 52 | xorl %eax, %eax |
| 53 | xorl %edx, %edx |
| 54 | clear_mtrrs: |
| 55 | movw (%esi), %bx |
| 56 | movzx %bx, %ecx |
| 57 | wrmsr |
| 58 | add $2, %esi |
| 59 | dec %edi |
| 60 | jnz clear_mtrrs |
| 61 | |
| 62 | /* Configure the default memory type to uncacheable. */ |
| 63 | movl $MTRRdefType_MSR, %ecx |
| 64 | rdmsr |
| 65 | andl $(~0x00000cff), %eax |
| 66 | wrmsr |
| 67 | |
| 68 | /* Set Cache-as-RAM base address. */ |
| 69 | movl $(MTRRphysBase_MSR(0)), %ecx |
| 70 | movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax |
| 71 | xorl %edx, %edx |
| 72 | wrmsr |
| 73 | |
| 74 | /* Set Cache-as-RAM mask. */ |
| 75 | movl $(MTRRphysMask_MSR(0)), %ecx |
| 76 | movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax |
| 77 | movl $CPU_PHYSMASK_HI, %edx |
| 78 | wrmsr |
| 79 | |
| 80 | /* Enable MTRR. */ |
| 81 | movl $MTRRdefType_MSR, %ecx |
| 82 | rdmsr |
| 83 | orl $MTRRdefTypeEn, %eax |
| 84 | wrmsr |
| 85 | |
Kyösti Mälkki | 05d6ffb | 2012-02-16 23:12:04 +0200 | [diff] [blame^] | 86 | /* Enable L2 cache Write-Back (WBINVD and FLUSH#). |
| 87 | * |
| 88 | * MSR is set when DisplayFamily_DisplayModel is one of: |
| 89 | * 06_0x, 06_17, 06_1C |
| 90 | * |
| 91 | * Description says this bit enables use of WBINVD and FLUSH#. |
| 92 | * Should this be set only after the system bus and/or memory |
| 93 | * controller can successfully handle write cycles? |
| 94 | */ |
| 95 | |
| 96 | #define EAX_FAMILY(a) (a << 8) /* for family <= 0fH */ |
| 97 | #define EAX_MODEL(a) (((a & 0xf0) << 12) | ((a & 0xf) << 4)) |
| 98 | |
| 99 | movl $1, %eax |
| 100 | cpuid |
| 101 | movl %eax, %ebx |
| 102 | andl $EAX_FAMILY(0x0f), %eax |
| 103 | cmpl $EAX_FAMILY(0x06), %eax |
| 104 | jne no_msr_11e |
| 105 | movl %ebx, %eax |
| 106 | andl $EAX_MODEL(0xff), %eax |
| 107 | cmpl $EAX_MODEL(0x17), %eax |
| 108 | je has_msr_11e |
| 109 | cmpl $EAX_MODEL(0x1c), %eax |
| 110 | je has_msr_11e |
| 111 | andl $EAX_MODEL(0xf0), %eax |
| 112 | cmpl $EAX_MODEL(0x00), %eax |
| 113 | jne no_msr_11e |
| 114 | has_msr_11e: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 115 | movl $0x11e, %ecx |
| 116 | rdmsr |
| 117 | orl $(1 << 8), %eax |
| 118 | wrmsr |
Kyösti Mälkki | 05d6ffb | 2012-02-16 23:12:04 +0200 | [diff] [blame^] | 119 | no_msr_11e: |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 120 | |
| 121 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 122 | movl %cr0, %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 123 | andl $(~((1 << 30) | (1 << 29))), %eax |
| 124 | invd |
| 125 | movl %eax, %cr0 |
| 126 | |
| 127 | /* Clear the cache memory reagion. */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 128 | cld |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 129 | xorl %eax, %eax |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 130 | movl $CACHE_AS_RAM_BASE, %edi |
| 131 | movl $(CACHE_AS_RAM_SIZE / 4), %ecx |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 132 | rep stosl |
| 133 | |
| 134 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 135 | movl %cr0, %eax |
| 136 | orl $(1 << 30), %eax |
| 137 | movl %eax, %cr0 |
| 138 | |
| 139 | #if CONFIG_XIP_ROM_SIZE |
| 140 | /* Enable cache for our code in Flash because we do XIP here */ |
| 141 | movl $MTRRphysBase_MSR(1), %ecx |
| 142 | xorl %edx, %edx |
| 143 | /* |
| 144 | * IMPORTANT: The following calculation _must_ be done at runtime. See |
| 145 | * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html |
| 146 | */ |
| 147 | movl $copy_and_run, %eax |
| 148 | andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax |
| 149 | orl $MTRR_TYPE_WRBACK, %eax |
| 150 | wrmsr |
| 151 | |
| 152 | movl $MTRRphysMask_MSR(1), %ecx |
| 153 | movl $CPU_PHYSMASK_HI, %edx |
| 154 | movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax |
| 155 | wrmsr |
| 156 | #endif /* CONFIG_XIP_ROM_SIZE */ |
| 157 | |
| 158 | /* Enable cache. */ |
| 159 | movl %cr0, %eax |
| 160 | andl $(~((1 << 30) | (1 << 29))), %eax |
| 161 | movl %eax, %cr0 |
| 162 | |
| 163 | /* Set up the stack pointer. */ |
| 164 | #if CONFIG_USBDEBUG |
| 165 | /* Leave some space for the struct ehci_debug_info. */ |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 166 | movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 167 | #else |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 168 | movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 169 | #endif |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 170 | |
| 171 | /* Restore the BIST result. */ |
| 172 | movl %ebp, %eax |
| 173 | movl %esp, %ebp |
| 174 | pushl %eax |
| 175 | |
| 176 | post_code(0x23) |
| 177 | |
| 178 | /* Call romstage.c main function. */ |
| 179 | call main |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 180 | addl $4, %esp |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 181 | |
| 182 | post_code(0x2f) |
| 183 | |
| 184 | post_code(0x30) |
| 185 | |
| 186 | /* Disable cache. */ |
| 187 | movl %cr0, %eax |
| 188 | orl $(1 << 30), %eax |
| 189 | movl %eax, %cr0 |
| 190 | |
| 191 | post_code(0x31) |
| 192 | |
| 193 | /* Disable MTRR. */ |
| 194 | movl $MTRRdefType_MSR, %ecx |
| 195 | rdmsr |
| 196 | andl $(~MTRRdefTypeEn), %eax |
| 197 | wrmsr |
| 198 | |
| 199 | post_code(0x31) |
| 200 | |
| 201 | invd |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 202 | |
| 203 | post_code(0x33) |
| 204 | |
| 205 | /* Enable cache. */ |
| 206 | movl %cr0, %eax |
| 207 | andl $~((1 << 30) | (1 << 29)), %eax |
| 208 | movl %eax, %cr0 |
| 209 | |
| 210 | post_code(0x36) |
| 211 | |
| 212 | /* Disable cache. */ |
| 213 | movl %cr0, %eax |
| 214 | orl $(1 << 30), %eax |
| 215 | movl %eax, %cr0 |
| 216 | |
| 217 | post_code(0x38) |
| 218 | |
Kyösti Mälkki | f9d1a42 | 2012-02-28 01:45:44 +0200 | [diff] [blame] | 219 | /* Enable Write Back and Speculative Reads for low RAM. */ |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 220 | movl $MTRRphysBase_MSR(0), %ecx |
| 221 | movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax |
| 222 | xorl %edx, %edx |
| 223 | wrmsr |
| 224 | movl $MTRRphysMask_MSR(0), %ecx |
| 225 | movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax |
| 226 | movl $CPU_PHYSMASK_HI, %edx |
| 227 | wrmsr |
| 228 | |
Kyösti Mälkki | 325b92f | 2012-02-28 00:24:15 +0200 | [diff] [blame] | 229 | /* Enable caching and Speculative Reads for Flash ROM device. */ |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 230 | movl $MTRRphysBase_MSR(1), %ecx |
Kyösti Mälkki | 325b92f | 2012-02-28 00:24:15 +0200 | [diff] [blame] | 231 | movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 232 | xorl %edx, %edx |
| 233 | wrmsr |
| 234 | movl $MTRRphysMask_MSR(1), %ecx |
Kyösti Mälkki | 325b92f | 2012-02-28 00:24:15 +0200 | [diff] [blame] | 235 | movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax |
Kyösti Mälkki | 5a660ca | 2012-02-28 00:15:30 +0200 | [diff] [blame] | 236 | movl $CPU_PHYSMASK_HI, %edx |
| 237 | wrmsr |
| 238 | |
| 239 | post_code(0x39) |
| 240 | |
| 241 | /* And enable cache again after setting MTRRs. */ |
| 242 | movl %cr0, %eax |
| 243 | andl $~((1 << 30) | (1 << 29)), %eax |
| 244 | movl %eax, %cr0 |
| 245 | |
| 246 | post_code(0x3a) |
| 247 | |
| 248 | /* Enable MTRR. */ |
| 249 | movl $MTRRdefType_MSR, %ecx |
| 250 | rdmsr |
| 251 | orl $MTRRdefTypeEn, %eax |
| 252 | wrmsr |
| 253 | |
| 254 | post_code(0x3b) |
| 255 | |
| 256 | /* Invalidate the cache again. */ |
| 257 | invd |
| 258 | |
| 259 | post_code(0x3c) |
| 260 | |
| 261 | /* Clear boot_complete flag. */ |
| 262 | xorl %ebp, %ebp |
| 263 | __main: |
| 264 | post_code(POST_PREPARE_RAMSTAGE) |
| 265 | cld /* Clear direction flag. */ |
| 266 | |
| 267 | movl %ebp, %esi |
| 268 | |
| 269 | movl $ROMSTAGE_STACK, %esp |
| 270 | movl %esp, %ebp |
| 271 | pushl %esi |
| 272 | call copy_and_run |
| 273 | |
| 274 | .Lhlt: |
| 275 | post_code(POST_DEAD_CODE) |
| 276 | hlt |
| 277 | jmp .Lhlt |
| 278 | |
| 279 | mtrr_table: |
| 280 | /* Fixed MTRRs */ |
| 281 | .word 0x250, 0x258, 0x259 |
| 282 | .word 0x268, 0x269, 0x26A |
| 283 | .word 0x26B, 0x26C, 0x26D |
| 284 | .word 0x26E, 0x26F |
| 285 | /* Variable MTRRs */ |
| 286 | .word 0x200, 0x201, 0x202, 0x203 |
| 287 | .word 0x204, 0x205, 0x206, 0x207 |
| 288 | .word 0x208, 0x209, 0x20A, 0x20B |
| 289 | .word 0x20C, 0x20D, 0x20E, 0x20F |
| 290 | mtrr_table_end: |
| 291 | |