Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 17 | #include <device/pci_def.h> |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 18 | #include <device/pnp_def.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 19 | #include <console/console.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 20 | #include <southbridge/intel/i82371eb/i82371eb.h> |
| 21 | #include <northbridge/intel/i440bx/raminit.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 22 | #include <cpu/x86/bist.h> |
Kyösti Mälkki | 07921540d | 2016-06-17 17:22:00 +0300 | [diff] [blame] | 23 | #include <cpu/intel/romstage.h> |
Edward O'Callaghan | 6fb379a | 2014-06-01 17:38:22 +1000 | [diff] [blame] | 24 | #include <superio/winbond/common/winbond.h> |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 25 | /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ |
Edward O'Callaghan | 6fb379a | 2014-06-01 17:38:22 +1000 | [diff] [blame] | 26 | #include <superio/winbond/w83977tf/w83977tf.h> |
Uwe Hermann | 6f2d20e | 2010-10-06 19:32:39 +0000 | [diff] [blame] | 27 | #include <lib.h> |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 28 | |
| 29 | /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ |
| 30 | #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) |
| 31 | |
Uwe Hermann | 115c5b9 | 2010-10-09 17:00:18 +0000 | [diff] [blame] | 32 | int spd_read_byte(unsigned int device, unsigned int address) |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 33 | { |
| 34 | return smbus_read_byte(device, address); |
| 35 | } |
| 36 | |
Uwe Hermann | 0865b4d | 2010-09-19 21:12:05 +0000 | [diff] [blame] | 37 | /* |
| 38 | * ASUS P3B-F specific SPD enable magic. |
| 39 | * |
| 40 | * Setting the byte at offset 0x37 in the PM I/O space to 0x6f will make the |
| 41 | * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD |
| 42 | * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which |
| 43 | * will make RAM init fail. |
| 44 | * |
| 45 | * Tested values for PM I/O offset 0x37: |
| 46 | * 0x67: 11 00 111: Only SMBus/I2C offsets 0x48/0x49/0x2d accessible |
| 47 | * 0x6f: 11 01 111: Only SMBus/I2C offsets 0x50-0x53 (SPD) accessible |
| 48 | * 0x77: 11 10 111: Only SMBus/I2C offset 0x69 accessible |
| 49 | * |
| 50 | * PM I/O space offset 0x37 is GPOREG[31:24], i.e. it controls the GPIOs |
| 51 | * 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28 |
| 52 | * control which SMBus/I2C offsets can be accessed. |
| 53 | */ |
| 54 | static void enable_spd(void) |
| 55 | { |
| 56 | outb(0x6f, PM_IO_BASE + 0x37); |
| 57 | } |
| 58 | |
| 59 | /* |
| 60 | * Disable SPD access after RAM init to allow access to SMBus/I2C offsets |
| 61 | * 0x48/0x49/0x2d, which is required e.g. by lm-sensors. |
| 62 | */ |
| 63 | static void disable_spd(void) |
| 64 | { |
| 65 | outb(0x67, PM_IO_BASE + 0x37); |
| 66 | } |
| 67 | |
Kyösti Mälkki | 07921540d | 2016-06-17 17:22:00 +0300 | [diff] [blame] | 68 | void mainboard_romstage_entry(unsigned long bist) |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 69 | { |
Edward O'Callaghan | 6fb379a | 2014-06-01 17:38:22 +1000 | [diff] [blame] | 70 | winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 71 | console_init(); |
| 72 | report_bist_failure(bist); |
Uwe Hermann | 9095092 | 2009-10-04 23:50:06 +0000 | [diff] [blame] | 73 | |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 74 | enable_smbus(); |
Uwe Hermann | 0865b4d | 2010-09-19 21:12:05 +0000 | [diff] [blame] | 75 | enable_pm(); |
| 76 | |
| 77 | enable_spd(); |
| 78 | |
Uwe Hermann | 6f2d20e | 2010-10-06 19:32:39 +0000 | [diff] [blame] | 79 | dump_spd_registers(); |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 80 | sdram_set_registers(); |
| 81 | sdram_set_spd_registers(); |
| 82 | sdram_enable(); |
Uwe Hermann | 0865b4d | 2010-09-19 21:12:05 +0000 | [diff] [blame] | 83 | |
| 84 | disable_spd(); |
Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 85 | } |