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review.coreboot.org / coreboot / ce22cd066bfa1c3c2c24ef6c6759620c52aeba22 / . / src / northbridge / intel / sandybridge / pei_data.h
blob: d317515cf0f03a9f07fd778abec1a29e355f60c3 [file] [log] [blame]
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]1/*
2 * coreboot UEFI PEI wrapper
3 *
4 * Copyright (c) 2011, Google Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * * Neither the name of Google Inc. nor the
15 * names of its contributors may be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef PEI_DATA_H
31#define PEI_DATA_H
32
Marc Jonese7ae96f2012-11-13 15:07:45 -0700[diff] [blame]33typedef struct {
34 uint16_t mode; // 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto
35 uint16_t hs_port_switch_mask; // 4 bit mask, 1: switchable, 0: not switchable
36 uint16_t preboot_support; // 0: No xHCI preOS driver, 1: xHCI preOS driver
37 uint16_t xhci_streams; // 0: Disable, 1: Enable
38} pch_usb3_controller_settings;
39
Vadim Bendebury48a4a7f2012-06-07 18:47:13 -0700[diff] [blame]40typedef void (*tx_byte_func)(unsigned char byte);
Stefan Reinauer1cc34162013-06-27 15:59:18 -0700[diff] [blame]41#define PEI_VERSION 6
Marc Jonese7ae96f2012-11-13 15:07:45 -0700[diff] [blame]42
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]43struct pei_data
44{
45 uint32_t pei_version;
46 uint32_t mchbar;
47 uint32_t dmibar;
48 uint32_t epbar;
49 uint32_t pciexbar;
50 uint16_t smbusbar;
51 uint32_t wdbbar;
52 uint32_t wdbsize;
53 uint32_t hpet_address;
54 uint32_t rcba;
55 uint32_t pmbase;
56 uint32_t gpiobase;
57 uint32_t thermalbase;
58 uint32_t system_type; // 0 Mobile, 1 Desktop/Server
59 uint32_t tseg_size;
60 uint8_t spd_addresses[4];
61 uint8_t ts_addresses[4];
62 int boot_mode;
63 int ec_present;
Stefan Reinauer1cc34162013-06-27 15:59:18 -0700[diff] [blame]64 int gbe_enable;
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]65 // 0 = leave channel enabled
66 // 1 = disable dimm 0 on channel
67 // 2 = disable dimm 1 on channel
68 // 3 = disable dimm 0+1 on channel
69 int dimm_channel0_disabled;
70 int dimm_channel1_disabled;
71 /* Seed values saved in CMOS */
72 uint32_t scrambler_seed;
73 uint32_t scrambler_seed_s3;
74 /* Data read from flash and passed into MRC */
75 unsigned char *mrc_input;
76 unsigned int mrc_input_len;
77 /* Data from MRC that should be saved to flash */
78 unsigned char *mrc_output;
79 unsigned int mrc_output_len;
80 /*
81 * Max frequency DDR3 could be ran at. Could be one of four values:
82 * 800, 1067, 1333, 1600
83 */
84 uint32_t max_ddr3_freq;
85 /*
86 * USB Port Configuration:
87 * [0] = enable
88 * [1] = overcurrent pin
89 * [2] = length
90 *
Marc Jones53508fe2012-07-11 16:30:28 -0600[diff] [blame]91 * Ports 0-7 can be mapped to OC0-OC3
92 * Ports 8-13 can be mapped to OC4-OC7
93 *
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]94 * Port Length
95 * MOBILE:
96 * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude)
97 * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude)
98 * DESKTOP:
99 * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude)
100 * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude)
101 * < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude)
102 */
103 uint16_t usb_port_config[16][3];
Marc Jonese7ae96f2012-11-13 15:07:45 -0700[diff] [blame]104 /* See the usb3 struct above for details */
105 pch_usb3_controller_settings usb3;
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]106 /* SPD data array for onboard RAM. Specify address 0xf0,
107 * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in
108 * spd_address for a given "DIMM".
109 */
110 uint8_t spd_data[4][256];
Vadim Bendebury48a4a7f2012-06-07 18:47:13 -0700[diff] [blame]111 tx_byte_func tx_byte;
Duncan Lauriee8179b52012-07-11 10:40:45 -0700[diff] [blame]112 int ddr3lv_support;
Stefan Reinauer7e8c8e92012-09-04 10:59:29 -0700[diff] [blame]113 /* pcie_init needs to be set to 1 to have the system agent initialize
114 * PCIe. Note: This should only be required if your system has Gen3 devices
115 * and it will increase your boot time by at least 100ms.
116 */
117 int pcie_init;
118 /* N mode functionality. Leave this setting at 0.
119 * 0 Auto
120 * 1 1N
121 * 2 2N
122 */
123 int nmode;
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]124} __attribute__((packed));
125
126#endif