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Angel Ponsf23ae0b2020-04-02 23:48:12 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Kyösti Mälkki48518f02014-11-25 14:20:57 +02002
Felix Held928a9c82022-02-24 00:51:11 +01003#include <arch/hpet.h>
Kyösti Mälkki48518f02014-11-25 14:20:57 +02004#include <cpu/x86/mtrr.h>
Elyes HAOUAS400ce552018-10-12 10:54:30 +02005#include <cpu/amd/msr.h>
Elyes HAOUAS8a643702018-10-23 17:10:27 +02006#include <cpu/amd/mtrr.h>
Kyösti Mälkkid610c582017-03-05 06:28:18 +02007#include <northbridge/amd/agesa/agesa_helper.h>
8#include <AGESA.h>
Elyes HAOUAS19f5ba82018-10-14 14:52:06 +02009#include <amdlib.h>
Kyösti Mälkki48518f02014-11-25 14:20:57 +020010
11void amd_initcpuio(void)
12{
13 UINT64 MsrReg;
14 UINT32 PciData;
15 PCI_ADDR PciAddress;
16 AMD_CONFIG_PARAMS StdHeader;
17
18 /* Enable legacy video routing: D18F1xF4 VGA Enable */
Frans Hendrikse5aafb62021-01-27 09:17:59 +010019 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
Kyösti Mälkki48518f02014-11-25 14:20:57 +020020 PciData = 1;
21 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
22
23 /* The platform BIOS needs to ensure the memory ranges of Hudson legacy
24 * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
25 * set to non-posted regions.
26 */
Frans Hendrikse5aafb62021-01-27 09:17:59 +010027 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
Kyösti Mälkki48518f02014-11-25 14:20:57 +020028 PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
29 PciData |= 1 << 7; /* set NP (non-posted) bit */
30 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Frans Hendrikse5aafb62021-01-27 09:17:59 +010031 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
Felix Held928a9c82022-02-24 00:51:11 +010032 PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */
Kyösti Mälkki48518f02014-11-25 14:20:57 +020033 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
34
35 /* Map the remaining PCI hole as posted MMIO */
Frans Hendrikse5aafb62021-01-27 09:17:59 +010036 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
Kyösti Mälkki48518f02014-11-25 14:20:57 +020037 PciData = 0x00FECF00; /* last address before non-posted range */
38 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Elyes HAOUAS8a643702018-10-23 17:10:27 +020039 LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
Kyösti Mälkki48518f02014-11-25 14:20:57 +020040 MsrReg = (MsrReg >> 8) | 3;
Frans Hendrikse5aafb62021-01-27 09:17:59 +010041 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
Kyösti Mälkki48518f02014-11-25 14:20:57 +020042 PciData = (UINT32)MsrReg;
43 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
44
45 /* Send all IO (0000-FFFF) to southbridge. */
Frans Hendrikse5aafb62021-01-27 09:17:59 +010046 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
Kyösti Mälkki48518f02014-11-25 14:20:57 +020047 PciData = 0x0000F000;
48 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Frans Hendrikse5aafb62021-01-27 09:17:59 +010049 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
Kyösti Mälkki48518f02014-11-25 14:20:57 +020050 PciData = 0x00000003;
51 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
52}