Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <cpu/x86/mtrr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame^] | 17 | #include <cpu/amd/msr.h> |
Kyösti Mälkki | d610c58 | 2017-03-05 06:28:18 +0200 | [diff] [blame] | 18 | #include <northbridge/amd/agesa/agesa_helper.h> |
| 19 | #include <AGESA.h> |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 20 | #include "amdlib.h" |
| 21 | |
| 22 | void amd_initcpuio(void) |
| 23 | { |
| 24 | UINT64 MsrReg; |
| 25 | UINT32 PciData; |
| 26 | PCI_ADDR PciAddress; |
| 27 | AMD_CONFIG_PARAMS StdHeader; |
| 28 | |
| 29 | /* Enable legacy video routing: D18F1xF4 VGA Enable */ |
| 30 | PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); |
| 31 | PciData = 1; |
| 32 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 33 | |
| 34 | /* The platform BIOS needs to ensure the memory ranges of Hudson legacy |
| 35 | * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are |
| 36 | * set to non-posted regions. |
| 37 | */ |
| 38 | PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); |
| 39 | PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ |
| 40 | PciData |= 1 << 7; /* set NP (non-posted) bit */ |
| 41 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 42 | PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); |
| 43 | PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ |
| 44 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 45 | |
| 46 | /* Map the remaining PCI hole as posted MMIO */ |
| 47 | PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); |
| 48 | PciData = 0x00FECF00; /* last address before non-posted range */ |
| 49 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 50 | LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); |
| 51 | MsrReg = (MsrReg >> 8) | 3; |
| 52 | PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); |
| 53 | PciData = (UINT32)MsrReg; |
| 54 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 55 | |
| 56 | /* Send all IO (0000-FFFF) to southbridge. */ |
| 57 | PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); |
| 58 | PciData = 0x0000F000; |
| 59 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 60 | PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); |
| 61 | PciData = 0x00000003; |
| 62 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 63 | } |
| 64 | |
| 65 | void amd_initmmio(void) |
| 66 | { |
| 67 | UINT64 MsrReg; |
| 68 | AMD_CONFIG_PARAMS StdHeader; |
| 69 | |
| 70 | /* |
| 71 | Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base |
| 72 | Address MSR register. |
| 73 | */ |
| 74 | MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame^] | 75 | LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 76 | |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 77 | /* Set ROM cache onto WP to decrease post time */ |
| 78 | MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; |
| 79 | LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); |
| 80 | MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; |
| 81 | LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); |
| 82 | } |