Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 2 | |
| 3 | #include <cpu/x86/mtrr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 4 | #include <cpu/amd/msr.h> |
Elyes HAOUAS | 8a64370 | 2018-10-23 17:10:27 +0200 | [diff] [blame] | 5 | #include <cpu/amd/mtrr.h> |
Kyösti Mälkki | d610c58 | 2017-03-05 06:28:18 +0200 | [diff] [blame] | 6 | #include <northbridge/amd/agesa/agesa_helper.h> |
| 7 | #include <AGESA.h> |
Elyes HAOUAS | 19f5ba8 | 2018-10-14 14:52:06 +0200 | [diff] [blame] | 8 | #include <amdlib.h> |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 9 | |
| 10 | void amd_initcpuio(void) |
| 11 | { |
| 12 | UINT64 MsrReg; |
| 13 | UINT32 PciData; |
| 14 | PCI_ADDR PciAddress; |
| 15 | AMD_CONFIG_PARAMS StdHeader; |
| 16 | |
| 17 | /* Enable legacy video routing: D18F1xF4 VGA Enable */ |
Frans Hendriks | e5aafb6 | 2021-01-27 09:17:59 +0100 | [diff] [blame] | 18 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 19 | PciData = 1; |
| 20 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 21 | |
| 22 | /* The platform BIOS needs to ensure the memory ranges of Hudson legacy |
| 23 | * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are |
| 24 | * set to non-posted regions. |
| 25 | */ |
Frans Hendriks | e5aafb6 | 2021-01-27 09:17:59 +0100 | [diff] [blame] | 26 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 27 | PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ |
| 28 | PciData |= 1 << 7; /* set NP (non-posted) bit */ |
| 29 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
Frans Hendriks | e5aafb6 | 2021-01-27 09:17:59 +0100 | [diff] [blame] | 30 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 31 | PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ |
| 32 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 33 | |
| 34 | /* Map the remaining PCI hole as posted MMIO */ |
Frans Hendriks | e5aafb6 | 2021-01-27 09:17:59 +0100 | [diff] [blame] | 35 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 36 | PciData = 0x00FECF00; /* last address before non-posted range */ |
| 37 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
Elyes HAOUAS | 8a64370 | 2018-10-23 17:10:27 +0200 | [diff] [blame] | 38 | LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 39 | MsrReg = (MsrReg >> 8) | 3; |
Frans Hendriks | e5aafb6 | 2021-01-27 09:17:59 +0100 | [diff] [blame] | 40 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 41 | PciData = (UINT32)MsrReg; |
| 42 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 43 | |
| 44 | /* Send all IO (0000-FFFF) to southbridge. */ |
Frans Hendriks | e5aafb6 | 2021-01-27 09:17:59 +0100 | [diff] [blame] | 45 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 46 | PciData = 0x0000F000; |
| 47 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
Frans Hendriks | e5aafb6 | 2021-01-27 09:17:59 +0100 | [diff] [blame] | 48 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); |
Kyösti Mälkki | 48518f0 | 2014-11-25 14:20:57 +0200 | [diff] [blame] | 49 | PciData = 0x00000003; |
| 50 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 51 | } |