Angel Pons | d28443e | 2020-04-05 13:22:44 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 2 | |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 3 | #include <stdint.h> |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 4 | #include <string.h> |
Angel Pons | 77ef99b | 2021-02-11 14:25:44 +0100 | [diff] [blame] | 5 | #include <ec/google/chromeec/ec.h> |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 6 | #include <northbridge/intel/haswell/raminit.h> |
| 7 | #include <southbridge/intel/lynxpoint/pch.h> |
| 8 | #include <southbridge/intel/lynxpoint/lp_gpio.h> |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 9 | #include "../../onboard.h" |
| 10 | #include "../../variant.h" |
| 11 | |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 12 | /* Copy SPD data for on-board memory */ |
Angel Pons | 6eea191 | 2020-07-03 14:14:30 +0200 | [diff] [blame] | 13 | void copy_spd(struct pei_data *peid) |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 14 | { |
| 15 | const int gpio_vector[] = {13, 9, 47, -1}; |
Angel Pons | 77ef99b | 2021-02-11 14:25:44 +0100 | [diff] [blame] | 16 | |
| 17 | unsigned int spd_index = fill_spd_for_index(peid->spd_data[0], get_gpios(gpio_vector)); |
| 18 | |
Karthikeyan Ramasubramanian | c80ff84 | 2018-09-17 16:19:34 -0600 | [diff] [blame] | 19 | uint32_t board_version = PEPPY_BOARD_VERSION_PROTO; |
Karthikeyan Ramasubramanian | c80ff84 | 2018-09-17 16:19:34 -0600 | [diff] [blame] | 20 | google_chromeec_get_board_version(&board_version); |
| 21 | switch (board_version) { |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 22 | case PEPPY_BOARD_VERSION_PROTO: |
| 23 | /* Index 0 is 2GB config with CH0 only. */ |
| 24 | if (spd_index == 0) |
| 25 | peid->dimm_channel1_disabled = 3; |
Matt DeVillier | cadd7c7 | 2017-05-29 19:10:57 -0500 | [diff] [blame] | 26 | else |
Angel Pons | afc6c0a | 2021-03-12 15:49:55 +0100 | [diff] [blame^] | 27 | memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN); |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 28 | break; |
| 29 | |
| 30 | case PEPPY_BOARD_VERSION_EVT: |
| 31 | default: |
Matt DeVillier | f41eea4 | 2019-12-26 20:10:32 -0600 | [diff] [blame] | 32 | /* Index 0-3 are 4GB config with both CH0 and CH1. |
| 33 | * Index 4-7 are 2GB config with CH0 only. */ |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 34 | if (spd_index > 3) |
| 35 | peid->dimm_channel1_disabled = 3; |
Matt DeVillier | cadd7c7 | 2017-05-29 19:10:57 -0500 | [diff] [blame] | 36 | else |
Angel Pons | afc6c0a | 2021-03-12 15:49:55 +0100 | [diff] [blame^] | 37 | memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN); |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 38 | break; |
| 39 | } |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 40 | } |
| 41 | |
Angel Pons | a3c6ed0 | 2021-02-11 13:59:12 +0100 | [diff] [blame] | 42 | const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { |
| 43 | /* Length, Enable, OCn#, Location */ |
| 44 | { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */ |
| 45 | USB_PORT_MINI_PCIE }, |
| 46 | { 0x0040, 1, 0, /* P1: Port A, CN10 */ |
| 47 | USB_PORT_BACK_PANEL }, |
| 48 | { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ |
| 49 | USB_PORT_INTERNAL }, |
| 50 | { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ |
| 51 | USB_PORT_MINI_PCIE }, |
| 52 | { 0x0040, 1, 2, /* P4: Port B, CN6 */ |
| 53 | USB_PORT_BACK_PANEL }, |
| 54 | { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */ |
| 55 | USB_PORT_SKIP }, |
| 56 | { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ |
| 57 | USB_PORT_FLEX }, |
| 58 | { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ |
| 59 | USB_PORT_SKIP }, |
| 60 | }; |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 61 | |
Angel Pons | a3c6ed0 | 2021-02-11 13:59:12 +0100 | [diff] [blame] | 62 | const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { |
| 63 | /* Enable, OCn# */ |
| 64 | { 1, 0 }, /* P1; Port A, CN6 */ |
| 65 | { 0, USB_OC_PIN_SKIP }, /* P2; */ |
| 66 | { 0, USB_OC_PIN_SKIP }, /* P3; */ |
| 67 | { 0, USB_OC_PIN_SKIP }, /* P4; */ |
| 68 | }; |