Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2012 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <delay.h> |
| 18 | #include <stdint.h> |
| 19 | #include <stdlib.h> |
| 20 | #include <string.h> |
| 21 | #include <cbfs.h> |
| 22 | #include <console/console.h> |
| 23 | #include <cpu/intel/haswell/haswell.h> |
| 24 | #include "ec/google/chromeec/ec.h" |
| 25 | #include <northbridge/intel/haswell/haswell.h> |
| 26 | #include <northbridge/intel/haswell/raminit.h> |
| 27 | #include <southbridge/intel/lynxpoint/pch.h> |
| 28 | #include <southbridge/intel/lynxpoint/lp_gpio.h> |
| 29 | #include <variant/gpio.h> |
| 30 | #include "../../onboard.h" |
| 31 | #include "../../variant.h" |
| 32 | |
| 33 | const struct rcba_config_instruction rcba_config[] = { |
| 34 | |
| 35 | /* |
| 36 | * GFX INTA -> PIRQA (MSI) |
| 37 | * D28IP_P1IP PCIE INTA -> PIRQA |
| 38 | * D29IP_E1P EHCI INTA -> PIRQD |
| 39 | * D20IP_XHCI XHCI INTA -> PIRQC (MSI) |
| 40 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 41 | * D31IP_SMIP SMBUS INTB -> PIRQG |
| 42 | * D31IP_TTIP THRT INTC -> PIRQA |
| 43 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 44 | */ |
| 45 | |
| 46 | /* Device interrupt pin register (board specific) */ |
| 47 | RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 48 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), |
| 49 | RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), |
| 50 | RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | |
| 51 | (INTB << D28IP_P4IP)), |
| 52 | RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), |
| 53 | RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), |
| 54 | RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), |
| 55 | RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), |
| 56 | |
| 57 | /* Device interrupt route registers */ |
| 58 | RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ |
| 59 | RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ |
| 60 | RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ |
| 61 | RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ |
| 62 | RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ |
| 63 | RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ |
| 64 | RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ |
| 65 | RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ |
| 66 | |
| 67 | /* Disable unused devices (board specific) */ |
| 68 | RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), |
| 69 | |
| 70 | RCBA_END_CONFIG, |
| 71 | }; |
| 72 | |
| 73 | /* Copy SPD data for on-board memory */ |
| 74 | static void copy_spd(struct pei_data *peid) |
| 75 | { |
| 76 | const int gpio_vector[] = {13, 9, 47, -1}; |
| 77 | int spd_index = get_gpios(gpio_vector); |
| 78 | char *spd_file; |
| 79 | size_t spd_file_len; |
| 80 | |
| 81 | printk(BIOS_DEBUG, "SPD index %d\n", spd_index); |
| 82 | spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, |
| 83 | &spd_file_len); |
| 84 | if (!spd_file) |
| 85 | die("SPD data not found."); |
| 86 | |
| 87 | switch (google_chromeec_get_board_version()) { |
| 88 | case PEPPY_BOARD_VERSION_PROTO: |
| 89 | /* Index 0 is 2GB config with CH0 only. */ |
| 90 | if (spd_index == 0) |
| 91 | peid->dimm_channel1_disabled = 3; |
| 92 | break; |
| 93 | |
| 94 | case PEPPY_BOARD_VERSION_EVT: |
| 95 | default: |
| 96 | /* Index 0-2 are 4GB config with both CH0 and CH1. |
| 97 | * Index 4-6 are 2GB config with CH0 only. */ |
| 98 | if (spd_index > 3) |
| 99 | peid->dimm_channel1_disabled = 3; |
| 100 | break; |
| 101 | } |
| 102 | |
| 103 | if (spd_file_len < |
| 104 | ((spd_index + 1) * sizeof(peid->spd_data[0]))) { |
| 105 | printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); |
| 106 | spd_index = 0; |
| 107 | } |
| 108 | |
| 109 | if (spd_file_len < sizeof(peid->spd_data[0])) |
| 110 | die("Missing SPD data."); |
| 111 | |
| 112 | memcpy(peid->spd_data[0], |
| 113 | spd_file + |
| 114 | spd_index * sizeof(peid->spd_data[0]), |
| 115 | sizeof(peid->spd_data[0])); |
| 116 | } |
| 117 | |
| 118 | void variant_romstage_entry(unsigned long bist) |
| 119 | { |
| 120 | struct pei_data pei_data = { |
| 121 | .pei_version = PEI_VERSION, |
| 122 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 123 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
| 124 | .epbar = DEFAULT_EPBAR, |
| 125 | .pciexbar = DEFAULT_PCIEXBAR, |
| 126 | .smbusbar = SMBUS_IO_BASE, |
| 127 | .wdbbar = 0x4000000, |
| 128 | .wdbsize = 0x1000, |
| 129 | .hpet_address = HPET_ADDR, |
| 130 | .rcba = (uintptr_t)DEFAULT_RCBA, |
| 131 | .pmbase = DEFAULT_PMBASE, |
| 132 | .gpiobase = DEFAULT_GPIOBASE, |
| 133 | .temp_mmio_base = 0xfed08000, |
| 134 | .system_type = 5, /* ULT */ |
| 135 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 136 | .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, |
| 137 | .ec_present = 1, |
| 138 | // 0 = leave channel enabled |
| 139 | // 1 = disable dimm 0 on channel |
| 140 | // 2 = disable dimm 1 on channel |
| 141 | // 3 = disable dimm 0+1 on channel |
| 142 | .dimm_channel0_disabled = 2, |
| 143 | .dimm_channel1_disabled = 2, |
| 144 | .max_ddr3_freq = 1600, |
| 145 | .usb_xhci_on_resume = 1, |
| 146 | .usb2_ports = { |
| 147 | /* Length, Enable, OCn#, Location */ |
| 148 | { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */ |
| 149 | USB_PORT_MINI_PCIE }, |
| 150 | { 0x0040, 1, 0, /* P1: Port A, CN10 */ |
| 151 | USB_PORT_BACK_PANEL }, |
| 152 | { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ |
| 153 | USB_PORT_INTERNAL }, |
| 154 | { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ |
| 155 | USB_PORT_MINI_PCIE }, |
| 156 | { 0x0040, 1, 2, /* P4: Port B, CN6 */ |
| 157 | USB_PORT_BACK_PANEL }, |
| 158 | { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */ |
| 159 | USB_PORT_SKIP }, |
| 160 | { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ |
| 161 | USB_PORT_FLEX }, |
| 162 | { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ |
| 163 | USB_PORT_SKIP }, |
| 164 | }, |
| 165 | .usb3_ports = { |
| 166 | /* Enable, OCn# */ |
| 167 | { 1, 0 }, /* P1; Port A, CN6 */ |
| 168 | { 0, USB_OC_PIN_SKIP }, /* P2; */ |
| 169 | { 0, USB_OC_PIN_SKIP }, /* P3; */ |
| 170 | { 0, USB_OC_PIN_SKIP }, /* P4; */ |
| 171 | }, |
| 172 | }; |
| 173 | |
| 174 | struct romstage_params romstage_params = { |
| 175 | .pei_data = &pei_data, |
| 176 | .gpio_map = &mainboard_gpio_map, |
| 177 | .rcba_config = &rcba_config[0], |
| 178 | .bist = bist, |
| 179 | .copy_spd = copy_spd, |
| 180 | }; |
| 181 | |
| 182 | /* Call into the real romstage main with this board's attributes. */ |
| 183 | romstage_common(&romstage_params); |
| 184 | } |