Angel Pons | d28443e | 2020-04-05 13:22:44 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 2 | |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 3 | #include <stdint.h> |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 4 | #include <string.h> |
| 5 | #include <cbfs.h> |
| 6 | #include <console/console.h> |
| 7 | #include <cpu/intel/haswell/haswell.h> |
| 8 | #include "ec/google/chromeec/ec.h" |
| 9 | #include <northbridge/intel/haswell/haswell.h> |
| 10 | #include <northbridge/intel/haswell/raminit.h> |
| 11 | #include <southbridge/intel/lynxpoint/pch.h> |
| 12 | #include <southbridge/intel/lynxpoint/lp_gpio.h> |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 13 | #include "../../onboard.h" |
| 14 | #include "../../variant.h" |
| 15 | |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 16 | /* Copy SPD data for on-board memory */ |
Angel Pons | 6eea191 | 2020-07-03 14:14:30 +0200 | [diff] [blame] | 17 | void copy_spd(struct pei_data *peid) |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 18 | { |
| 19 | const int gpio_vector[] = {13, 9, 47, -1}; |
| 20 | int spd_index = get_gpios(gpio_vector); |
| 21 | char *spd_file; |
| 22 | size_t spd_file_len; |
Matt DeVillier | cadd7c7 | 2017-05-29 19:10:57 -0500 | [diff] [blame] | 23 | size_t spd_len = sizeof(peid->spd_data[0]); |
Karthikeyan Ramasubramanian | c80ff84 | 2018-09-17 16:19:34 -0600 | [diff] [blame] | 24 | uint32_t board_version = PEPPY_BOARD_VERSION_PROTO; |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 25 | |
| 26 | printk(BIOS_DEBUG, "SPD index %d\n", spd_index); |
Julius Werner | 834b3ec | 2020-03-04 16:52:08 -0800 | [diff] [blame] | 27 | spd_file = cbfs_map("spd.bin", &spd_file_len); |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 28 | if (!spd_file) |
| 29 | die("SPD data not found."); |
| 30 | |
Matt DeVillier | cadd7c7 | 2017-05-29 19:10:57 -0500 | [diff] [blame] | 31 | if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { |
| 32 | printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); |
| 33 | spd_index = 0; |
| 34 | } |
| 35 | |
| 36 | if (spd_file_len < spd_len) |
| 37 | die("Missing SPD data."); |
| 38 | |
| 39 | memcpy(peid->spd_data[0], spd_file + (spd_index * spd_len), spd_len); |
| 40 | |
Karthikeyan Ramasubramanian | c80ff84 | 2018-09-17 16:19:34 -0600 | [diff] [blame] | 41 | google_chromeec_get_board_version(&board_version); |
| 42 | switch (board_version) { |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 43 | case PEPPY_BOARD_VERSION_PROTO: |
| 44 | /* Index 0 is 2GB config with CH0 only. */ |
| 45 | if (spd_index == 0) |
| 46 | peid->dimm_channel1_disabled = 3; |
Matt DeVillier | cadd7c7 | 2017-05-29 19:10:57 -0500 | [diff] [blame] | 47 | else |
| 48 | memcpy(peid->spd_data[1], |
| 49 | spd_file + (spd_index * spd_len), spd_len); |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 50 | break; |
| 51 | |
| 52 | case PEPPY_BOARD_VERSION_EVT: |
| 53 | default: |
Matt DeVillier | f41eea4 | 2019-12-26 20:10:32 -0600 | [diff] [blame] | 54 | /* Index 0-3 are 4GB config with both CH0 and CH1. |
| 55 | * Index 4-7 are 2GB config with CH0 only. */ |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 56 | if (spd_index > 3) |
| 57 | peid->dimm_channel1_disabled = 3; |
Matt DeVillier | cadd7c7 | 2017-05-29 19:10:57 -0500 | [diff] [blame] | 58 | else |
| 59 | memcpy(peid->spd_data[1], |
| 60 | spd_file + (spd_index * spd_len), spd_len); |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 61 | break; |
| 62 | } |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 63 | } |
| 64 | |
Angel Pons | a3c6ed0 | 2021-02-11 13:59:12 +0100 | [diff] [blame^] | 65 | const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { |
| 66 | /* Length, Enable, OCn#, Location */ |
| 67 | { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */ |
| 68 | USB_PORT_MINI_PCIE }, |
| 69 | { 0x0040, 1, 0, /* P1: Port A, CN10 */ |
| 70 | USB_PORT_BACK_PANEL }, |
| 71 | { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ |
| 72 | USB_PORT_INTERNAL }, |
| 73 | { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ |
| 74 | USB_PORT_MINI_PCIE }, |
| 75 | { 0x0040, 1, 2, /* P4: Port B, CN6 */ |
| 76 | USB_PORT_BACK_PANEL }, |
| 77 | { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */ |
| 78 | USB_PORT_SKIP }, |
| 79 | { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ |
| 80 | USB_PORT_FLEX }, |
| 81 | { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ |
| 82 | USB_PORT_SKIP }, |
| 83 | }; |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 84 | |
Angel Pons | a3c6ed0 | 2021-02-11 13:59:12 +0100 | [diff] [blame^] | 85 | const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { |
| 86 | /* Enable, OCn# */ |
| 87 | { 1, 0 }, /* P1; Port A, CN6 */ |
| 88 | { 0, USB_OC_PIN_SKIP }, /* P2; */ |
| 89 | { 0, USB_OC_PIN_SKIP }, /* P3; */ |
| 90 | { 0, USB_OC_PIN_SKIP }, /* P4; */ |
| 91 | }; |