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Felix Helddc2d3562020-12-02 14:38:53 +01001/* SPDX-License-Identifier: GPL-2.0-only */
2
Fred Reitberger31e62982022-10-31 14:18:20 -04003#include <amdblocks/data_fabric.h>
Felix Held51c4d682021-02-16 23:14:42 +01004#include <console/console.h>
Felix Helddc2d3562020-12-02 14:38:53 +01005#include <device/device.h>
Felix Held51c4d682021-02-16 23:14:42 +01006#include <device/pci.h>
Felix Held86c24a22021-01-28 23:07:48 +01007#include <fsp/api.h>
Felix Held144c7aa2021-05-04 21:06:04 +02008#include <soc/acpi.h>
Jason Glenesk79542fa2021-03-10 03:50:57 -08009#include <soc/cpu.h>
Felix Held51c4d682021-02-16 23:14:42 +010010#include <soc/pci_devs.h>
Felix Held230dbd62021-01-28 23:40:52 +010011#include <soc/southbridge.h>
Felix Held86c24a22021-01-28 23:07:48 +010012#include <types.h>
Felix Heldc8272782020-12-05 01:39:28 +010013#include "chip.h"
Felix Helddc2d3562020-12-02 14:38:53 +010014
Felix Held51c4d682021-02-16 23:14:42 +010015static const char *soc_acpi_name(const struct device *dev)
16{
17 if (dev->path.type == DEVICE_PATH_DOMAIN)
18 return "PCI0";
19
20 if (dev->path.type != DEVICE_PATH_PCI)
21 return NULL;
22
23 printk(BIOS_WARNING, "Unknown PCI device: dev: %d, fn: %d\n",
24 PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
25 return NULL;
26};
27
Arthur Heymans7f380772022-09-20 14:03:28 +020028struct device_operations cezanne_pci_domain_ops = {
Felix Held9adc33d2023-05-31 16:08:42 +020029 .read_resources = amd_pci_domain_read_resources,
Felix Held5a7e4a52021-02-05 21:46:53 +010030 .set_resources = pci_domain_set_resources,
Felix Held9adc33d2023-05-31 16:08:42 +020031 .scan_bus = amd_pci_domain_scan_bus,
Felix Held51c4d682021-02-16 23:14:42 +010032 .acpi_name = soc_acpi_name,
Felix Held9adc33d2023-05-31 16:08:42 +020033 .acpi_fill_ssdt = amd_pci_domain_fill_ssdt,
Felix Held5a7e4a52021-02-05 21:46:53 +010034};
35
Felix Held613f9fc2021-01-26 18:09:46 +010036static void soc_init(void *chip_info)
37{
Felix Held144c7aa2021-05-04 21:06:04 +020038 default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
39
Kyösti Mälkkicc93c6e2021-01-09 22:53:52 +020040 fsp_silicon_init();
Felix Held230dbd62021-01-28 23:40:52 +010041
Felix Heldea32c522021-02-13 01:42:44 +010042 data_fabric_set_mmio_np();
43
Felix Held230dbd62021-01-28 23:40:52 +010044 fch_init(chip_info);
Felix Held613f9fc2021-01-26 18:09:46 +010045}
46
47static void soc_final(void *chip_info)
48{
Felix Held230dbd62021-01-28 23:40:52 +010049 fch_final(chip_info);
Felix Held613f9fc2021-01-26 18:09:46 +010050}
51
52struct chip_operations soc_amd_cezanne_ops = {
53 CHIP_NAME("AMD Cezanne SoC")
Felix Held613f9fc2021-01-26 18:09:46 +010054 .init = soc_init,
55 .final = soc_final
56};