Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #include <types.h> |
| 4 | #include <console/console.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpi.h> |
| 6 | #include <acpi/acpigen.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 7 | #include <arch/cpu.h> |
| 8 | #include <cpu/x86/msr.h> |
| 9 | #include <cpu/intel/speedstep.h> |
| 10 | #include <cpu/intel/turbo.h> |
| 11 | #include <device/device.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 12 | #include "haswell.h" |
| 13 | #include "chip.h" |
| 14 | |
Duncan Laurie | 1ad5564 | 2013-03-07 14:08:04 -0800 | [diff] [blame] | 15 | #include <southbridge/intel/lynxpoint/pch.h> |
| 16 | |
Angel Pons | ba5761a | 2020-10-28 18:50:26 +0100 | [diff] [blame] | 17 | static int cstate_set_lp[3] = { |
Angel Pons | bda1c55 | 2020-10-29 00:08:24 +0100 | [diff] [blame] | 18 | C_STATE_C1E, |
| 19 | C_STATE_C3, |
| 20 | C_STATE_C7S_LONG_LAT, |
Angel Pons | ba5761a | 2020-10-28 18:50:26 +0100 | [diff] [blame] | 21 | }; |
| 22 | |
| 23 | static int cstate_set_trad[3] = { |
Angel Pons | bda1c55 | 2020-10-29 00:08:24 +0100 | [diff] [blame] | 24 | C_STATE_C1, |
| 25 | C_STATE_C3, |
| 26 | C_STATE_C6_LONG_LAT, |
Angel Pons | ba5761a | 2020-10-28 18:50:26 +0100 | [diff] [blame] | 27 | }; |
| 28 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 29 | static int get_cores_per_package(void) |
| 30 | { |
| 31 | struct cpuinfo_x86 c; |
| 32 | struct cpuid_result result; |
| 33 | int cores = 1; |
| 34 | |
| 35 | get_fms(&c, cpuid_eax(1)); |
| 36 | if (c.x86 != 6) |
| 37 | return 1; |
| 38 | |
| 39 | result = cpuid_ext(0xb, 1); |
| 40 | cores = result.ebx & 0xff; |
| 41 | |
| 42 | return cores; |
| 43 | } |
| 44 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 45 | static acpi_tstate_t tss_table_fine[] = { |
| 46 | { 100, 1000, 0, 0x00, 0 }, |
| 47 | { 94, 940, 0, 0x1f, 0 }, |
| 48 | { 88, 880, 0, 0x1e, 0 }, |
| 49 | { 82, 820, 0, 0x1d, 0 }, |
| 50 | { 75, 760, 0, 0x1c, 0 }, |
| 51 | { 69, 700, 0, 0x1b, 0 }, |
| 52 | { 63, 640, 0, 0x1a, 0 }, |
| 53 | { 57, 580, 0, 0x19, 0 }, |
| 54 | { 50, 520, 0, 0x18, 0 }, |
| 55 | { 44, 460, 0, 0x17, 0 }, |
| 56 | { 38, 400, 0, 0x16, 0 }, |
| 57 | { 32, 340, 0, 0x15, 0 }, |
| 58 | { 25, 280, 0, 0x14, 0 }, |
| 59 | { 19, 220, 0, 0x13, 0 }, |
| 60 | { 13, 160, 0, 0x12, 0 }, |
| 61 | }; |
| 62 | |
| 63 | static acpi_tstate_t tss_table_coarse[] = { |
| 64 | { 100, 1000, 0, 0x00, 0 }, |
| 65 | { 88, 875, 0, 0x1f, 0 }, |
| 66 | { 75, 750, 0, 0x1e, 0 }, |
| 67 | { 63, 625, 0, 0x1d, 0 }, |
| 68 | { 50, 500, 0, 0x1c, 0 }, |
| 69 | { 38, 375, 0, 0x1b, 0 }, |
| 70 | { 25, 250, 0, 0x1a, 0 }, |
| 71 | { 13, 125, 0, 0x19, 0 }, |
| 72 | }; |
| 73 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 74 | static void generate_T_state_entries(int core, int cores_per_package) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 75 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 76 | /* Indicate SW_ALL coordination for T-states */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 77 | acpigen_write_TSD_package(core, cores_per_package, SW_ALL); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 78 | |
| 79 | /* Indicate FFixedHW so OS will use MSR */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 80 | acpigen_write_empty_PTC(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 81 | |
| 82 | /* Set a T-state limit that can be modified in NVS */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 83 | acpigen_write_TPC("\\TLVL"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 84 | |
| 85 | /* |
| 86 | * CPUID.(EAX=6):EAX[5] indicates support |
| 87 | * for extended throttle levels. |
| 88 | */ |
| 89 | if (cpuid_eax(6) & (1 << 5)) |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 90 | acpigen_write_TSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 91 | ARRAY_SIZE(tss_table_fine), tss_table_fine); |
| 92 | else |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 93 | acpigen_write_TSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 94 | ARRAY_SIZE(tss_table_coarse), tss_table_coarse); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 95 | } |
| 96 | |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 97 | static void generate_C_state_entries(void) |
| 98 | { |
Angel Pons | ba5761a | 2020-10-28 18:50:26 +0100 | [diff] [blame] | 99 | acpi_cstate_t map[3]; |
| 100 | int *set; |
| 101 | int i; |
| 102 | |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 103 | struct cpu_info *info; |
| 104 | struct cpu_driver *cpu; |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 105 | |
| 106 | /* Find CPU map of supported C-states */ |
| 107 | info = cpu_info(); |
| 108 | if (!info) |
| 109 | return; |
| 110 | cpu = find_cpu_driver(info->cpu); |
| 111 | if (!cpu || !cpu->cstates) |
| 112 | return; |
| 113 | |
Angel Pons | ba5761a | 2020-10-28 18:50:26 +0100 | [diff] [blame] | 114 | if (haswell_is_ult()) |
| 115 | set = cstate_set_lp; |
| 116 | else |
| 117 | set = cstate_set_trad; |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 118 | |
Angel Pons | ba5761a | 2020-10-28 18:50:26 +0100 | [diff] [blame] | 119 | for (i = 0; i < ARRAY_SIZE(map); i++) { |
| 120 | map[i] = cpu->cstates[set[i]]; |
| 121 | map[i].ctype = i + 1; |
| 122 | } |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 123 | |
Angel Pons | ba5761a | 2020-10-28 18:50:26 +0100 | [diff] [blame] | 124 | /* Generate C-state tables */ |
| 125 | acpigen_write_CST_package(map, ARRAY_SIZE(map)); |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 126 | } |
| 127 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 128 | static int calculate_power(int tdp, int p1_ratio, int ratio) |
| 129 | { |
| 130 | u32 m; |
| 131 | u32 power; |
| 132 | |
| 133 | /* |
| 134 | * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 |
| 135 | * |
| 136 | * Power = (ratio / p1_ratio) * m * tdp |
| 137 | */ |
| 138 | |
| 139 | m = (110000 - ((p1_ratio - ratio) * 625)) / 11; |
| 140 | m = (m * m) / 1000; |
| 141 | |
| 142 | power = ((ratio * 100000 / p1_ratio) / 100); |
| 143 | power *= (m / 100) * (tdp / 1000); |
| 144 | power /= 1000; |
| 145 | |
| 146 | return (int)power; |
| 147 | } |
| 148 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 149 | static void generate_P_state_entries(int core, int cores_per_package) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 150 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 151 | int ratio_min, ratio_max, ratio_turbo, ratio_step; |
| 152 | int coord_type, power_max, power_unit, num_entries; |
| 153 | int ratio, power, clock, clock_max; |
| 154 | msr_t msr; |
| 155 | |
| 156 | /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ |
| 157 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 158 | if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) |
| 159 | coord_type = SW_ANY; |
| 160 | else |
| 161 | coord_type = HW_ALL; |
| 162 | |
| 163 | /* Get bus ratio limits and calculate clock speeds */ |
| 164 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 165 | ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ |
| 166 | |
| 167 | /* Determine if this CPU has configurable TDP */ |
| 168 | if (cpu_config_tdp_levels()) { |
| 169 | /* Set max ratio to nominal TDP ratio */ |
| 170 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 171 | ratio_max = msr.lo & 0xff; |
| 172 | } else { |
| 173 | /* Max Non-Turbo Ratio */ |
| 174 | ratio_max = (msr.lo >> 8) & 0xff; |
| 175 | } |
Angel Pons | ca96549 | 2020-10-28 19:15:36 +0100 | [diff] [blame] | 176 | clock_max = ratio_max * CPU_BCLK; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 177 | |
| 178 | /* Calculate CPU TDP in mW */ |
| 179 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 180 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 181 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 182 | power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; |
| 183 | |
| 184 | /* Write _PCT indicating use of FFixedHW */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 185 | acpigen_write_empty_PCT(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 186 | |
| 187 | /* Write _PPC with no limit on supported P-state */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 188 | acpigen_write_PPC_NVS(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 189 | |
| 190 | /* Write PSD indicating configured coordination type */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 191 | acpigen_write_PSD_package(core, 1, coord_type); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 192 | |
| 193 | /* Add P-state entries in _PSS table */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 194 | acpigen_write_name("_PSS"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 195 | |
| 196 | /* Determine ratio points */ |
| 197 | ratio_step = PSS_RATIO_STEP; |
| 198 | num_entries = (ratio_max - ratio_min) / ratio_step; |
| 199 | while (num_entries > PSS_MAX_ENTRIES-1) { |
| 200 | ratio_step <<= 1; |
| 201 | num_entries >>= 1; |
| 202 | } |
| 203 | |
| 204 | /* P[T] is Turbo state if enabled */ |
| 205 | if (get_turbo_state() == TURBO_ENABLED) { |
| 206 | /* _PSS package count including Turbo */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 207 | acpigen_write_package(num_entries + 2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 208 | |
| 209 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 210 | ratio_turbo = msr.lo & 0xff; |
| 211 | |
| 212 | /* Add entry for Turbo ratio */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 213 | acpigen_write_PSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 214 | clock_max + 1, /*MHz*/ |
| 215 | power_max, /*mW*/ |
| 216 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 217 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 218 | ratio_turbo << 8, /*control*/ |
| 219 | ratio_turbo << 8); /*status*/ |
| 220 | } else { |
| 221 | /* _PSS package count without Turbo */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 222 | acpigen_write_package(num_entries + 1); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 223 | } |
| 224 | |
| 225 | /* First regular entry is max non-turbo ratio */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 226 | acpigen_write_PSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 227 | clock_max, /*MHz*/ |
| 228 | power_max, /*mW*/ |
| 229 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 230 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 231 | ratio_max << 8, /*control*/ |
| 232 | ratio_max << 8); /*status*/ |
| 233 | |
| 234 | /* Generate the remaining entries */ |
| 235 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 236 | ratio >= ratio_min; ratio -= ratio_step) { |
| 237 | |
| 238 | /* Calculate power at this ratio */ |
| 239 | power = calculate_power(power_max, ratio_max, ratio); |
Angel Pons | ca96549 | 2020-10-28 19:15:36 +0100 | [diff] [blame] | 240 | clock = ratio * CPU_BCLK; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 241 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 242 | acpigen_write_PSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 243 | clock, /*MHz*/ |
| 244 | power, /*mW*/ |
| 245 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 246 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 247 | ratio << 8, /*control*/ |
| 248 | ratio << 8); /*status*/ |
| 249 | } |
| 250 | |
| 251 | /* Fix package length */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 252 | acpigen_pop_len(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 253 | } |
| 254 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 255 | void generate_cpu_entries(const struct device *device) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 256 | { |
Duncan Laurie | 1ad5564 | 2013-03-07 14:08:04 -0800 | [diff] [blame] | 257 | int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 258 | int totalcores = dev_count_cpu(); |
| 259 | int cores_per_package = get_cores_per_package(); |
| 260 | int numcpus = totalcores/cores_per_package; |
| 261 | |
| 262 | printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", |
| 263 | numcpus, cores_per_package); |
| 264 | |
Martin Roth | 9944b28 | 2014-08-11 11:24:55 -0600 | [diff] [blame] | 265 | for (cpuID = 1; cpuID <= numcpus; cpuID++) { |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 266 | for (coreID = 1; coreID <= cores_per_package; coreID++) { |
| 267 | if (coreID > 1) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 268 | pcontrol_blk = 0; |
| 269 | plen = 0; |
| 270 | } |
| 271 | |
Christian Walter | be3979c | 2019-12-18 15:07:59 +0100 | [diff] [blame] | 272 | /* Generate processor \_SB.CPUx */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 273 | acpigen_write_processor( |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 274 | (cpuID - 1) * cores_per_package+coreID - 1, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 275 | pcontrol_blk, plen); |
| 276 | |
| 277 | /* Generate P-state tables */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 278 | generate_P_state_entries( |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 279 | coreID - 1, cores_per_package); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 280 | |
| 281 | /* Generate C-state tables */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 282 | generate_C_state_entries(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 283 | |
| 284 | /* Generate T-state tables */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 285 | generate_T_state_entries( |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 286 | cpuID - 1, cores_per_package); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 287 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 288 | acpigen_pop_len(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 289 | } |
| 290 | } |
Arthur Heymans | c54d14f | 2018-11-28 12:09:23 +0100 | [diff] [blame] | 291 | |
| 292 | /* PPKG is usually used for thermal management |
| 293 | of the first and only package. */ |
| 294 | acpigen_write_processor_package("PPKG", 0, cores_per_package); |
| 295 | |
| 296 | /* Add a method to notify processor nodes */ |
| 297 | acpigen_write_processor_cnot(cores_per_package); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 298 | } |
| 299 | |
| 300 | struct chip_operations cpu_intel_haswell_ops = { |
| 301 | CHIP_NAME("Intel Haswell CPU") |
| 302 | }; |