Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <types.h> |
| 19 | #include <console/console.h> |
| 20 | #include <arch/acpi.h> |
| 21 | #include <arch/acpigen.h> |
| 22 | #include <arch/cpu.h> |
| 23 | #include <cpu/x86/msr.h> |
| 24 | #include <cpu/intel/speedstep.h> |
| 25 | #include <cpu/intel/turbo.h> |
| 26 | #include <device/device.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 27 | #include "haswell.h" |
| 28 | #include "chip.h" |
| 29 | |
Duncan Laurie | 1ad5564 | 2013-03-07 14:08:04 -0800 | [diff] [blame] | 30 | #include <southbridge/intel/lynxpoint/pch.h> |
| 31 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 32 | static int get_cores_per_package(void) |
| 33 | { |
| 34 | struct cpuinfo_x86 c; |
| 35 | struct cpuid_result result; |
| 36 | int cores = 1; |
| 37 | |
| 38 | get_fms(&c, cpuid_eax(1)); |
| 39 | if (c.x86 != 6) |
| 40 | return 1; |
| 41 | |
| 42 | result = cpuid_ext(0xb, 1); |
| 43 | cores = result.ebx & 0xff; |
| 44 | |
| 45 | return cores; |
| 46 | } |
| 47 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 48 | static void generate_cstate_entries(acpi_cstate_t *cstates, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 49 | int c1, int c2, int c3) |
| 50 | { |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 51 | int cstate_count = 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 52 | |
| 53 | /* Count number of active C-states */ |
| 54 | if (c1 > 0) |
| 55 | ++cstate_count; |
| 56 | if (c2 > 0) |
| 57 | ++cstate_count; |
| 58 | if (c3 > 0) |
| 59 | ++cstate_count; |
| 60 | if (!cstate_count) |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 61 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 62 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 63 | acpigen_write_package(cstate_count + 1); |
| 64 | acpigen_write_byte(cstate_count); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 65 | |
| 66 | /* Add an entry if the level is enabled */ |
| 67 | if (c1 > 0) { |
| 68 | cstates[c1].ctype = 1; |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 69 | acpigen_write_CST_package_entry(&cstates[c1]); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 70 | } |
| 71 | if (c2 > 0) { |
| 72 | cstates[c2].ctype = 2; |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 73 | acpigen_write_CST_package_entry(&cstates[c2]); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 74 | } |
| 75 | if (c3 > 0) { |
| 76 | cstates[c3].ctype = 3; |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 77 | acpigen_write_CST_package_entry(&cstates[c3]); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 78 | } |
| 79 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 80 | acpigen_pop_len(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 81 | } |
| 82 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 83 | static void generate_C_state_entries(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 84 | { |
| 85 | struct cpu_info *info; |
| 86 | struct cpu_driver *cpu; |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 87 | struct device *lapic; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 88 | struct cpu_intel_haswell_config *conf = NULL; |
| 89 | |
| 90 | /* Find the SpeedStep CPU in the device tree using magic APIC ID */ |
| 91 | lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); |
| 92 | if (!lapic) |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 93 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 94 | conf = lapic->chip_info; |
| 95 | if (!conf) |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 96 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 97 | |
| 98 | /* Find CPU map of supported C-states */ |
| 99 | info = cpu_info(); |
| 100 | if (!info) |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 101 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 102 | cpu = find_cpu_driver(info->cpu); |
| 103 | if (!cpu || !cpu->cstates) |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 104 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 105 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 106 | acpigen_emit_byte(0x14); /* MethodOp */ |
| 107 | acpigen_write_len_f(); /* PkgLength */ |
| 108 | acpigen_emit_namestring("_CST"); |
| 109 | acpigen_emit_byte(0x00); /* No Arguments */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 110 | |
| 111 | /* If running on AC power */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 112 | acpigen_emit_byte(0xa0); /* IfOp */ |
| 113 | acpigen_write_len_f(); /* PkgLength */ |
| 114 | acpigen_emit_namestring("PWRS"); |
| 115 | acpigen_emit_byte(0xa4); /* ReturnOp */ |
| 116 | generate_cstate_entries(cpu->cstates, conf->c1_acpower, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 117 | conf->c2_acpower, conf->c3_acpower); |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 118 | acpigen_pop_len(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 119 | |
| 120 | /* Else on battery power */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 121 | acpigen_emit_byte(0xa4); /* ReturnOp */ |
| 122 | generate_cstate_entries(cpu->cstates, conf->c1_battery, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 123 | conf->c2_battery, conf->c3_battery); |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 124 | acpigen_pop_len(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 125 | } |
| 126 | |
| 127 | static acpi_tstate_t tss_table_fine[] = { |
| 128 | { 100, 1000, 0, 0x00, 0 }, |
| 129 | { 94, 940, 0, 0x1f, 0 }, |
| 130 | { 88, 880, 0, 0x1e, 0 }, |
| 131 | { 82, 820, 0, 0x1d, 0 }, |
| 132 | { 75, 760, 0, 0x1c, 0 }, |
| 133 | { 69, 700, 0, 0x1b, 0 }, |
| 134 | { 63, 640, 0, 0x1a, 0 }, |
| 135 | { 57, 580, 0, 0x19, 0 }, |
| 136 | { 50, 520, 0, 0x18, 0 }, |
| 137 | { 44, 460, 0, 0x17, 0 }, |
| 138 | { 38, 400, 0, 0x16, 0 }, |
| 139 | { 32, 340, 0, 0x15, 0 }, |
| 140 | { 25, 280, 0, 0x14, 0 }, |
| 141 | { 19, 220, 0, 0x13, 0 }, |
| 142 | { 13, 160, 0, 0x12, 0 }, |
| 143 | }; |
| 144 | |
| 145 | static acpi_tstate_t tss_table_coarse[] = { |
| 146 | { 100, 1000, 0, 0x00, 0 }, |
| 147 | { 88, 875, 0, 0x1f, 0 }, |
| 148 | { 75, 750, 0, 0x1e, 0 }, |
| 149 | { 63, 625, 0, 0x1d, 0 }, |
| 150 | { 50, 500, 0, 0x1c, 0 }, |
| 151 | { 38, 375, 0, 0x1b, 0 }, |
| 152 | { 25, 250, 0, 0x1a, 0 }, |
| 153 | { 13, 125, 0, 0x19, 0 }, |
| 154 | }; |
| 155 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 156 | static void generate_T_state_entries(int core, int cores_per_package) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 157 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 158 | /* Indicate SW_ALL coordination for T-states */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 159 | acpigen_write_TSD_package(core, cores_per_package, SW_ALL); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 160 | |
| 161 | /* Indicate FFixedHW so OS will use MSR */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 162 | acpigen_write_empty_PTC(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 163 | |
| 164 | /* Set a T-state limit that can be modified in NVS */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 165 | acpigen_write_TPC("\\TLVL"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 166 | |
| 167 | /* |
| 168 | * CPUID.(EAX=6):EAX[5] indicates support |
| 169 | * for extended throttle levels. |
| 170 | */ |
| 171 | if (cpuid_eax(6) & (1 << 5)) |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 172 | acpigen_write_TSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 173 | ARRAY_SIZE(tss_table_fine), tss_table_fine); |
| 174 | else |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 175 | acpigen_write_TSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 176 | ARRAY_SIZE(tss_table_coarse), tss_table_coarse); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | static int calculate_power(int tdp, int p1_ratio, int ratio) |
| 180 | { |
| 181 | u32 m; |
| 182 | u32 power; |
| 183 | |
| 184 | /* |
| 185 | * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 |
| 186 | * |
| 187 | * Power = (ratio / p1_ratio) * m * tdp |
| 188 | */ |
| 189 | |
| 190 | m = (110000 - ((p1_ratio - ratio) * 625)) / 11; |
| 191 | m = (m * m) / 1000; |
| 192 | |
| 193 | power = ((ratio * 100000 / p1_ratio) / 100); |
| 194 | power *= (m / 100) * (tdp / 1000); |
| 195 | power /= 1000; |
| 196 | |
| 197 | return (int)power; |
| 198 | } |
| 199 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 200 | static void generate_P_state_entries(int core, int cores_per_package) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 201 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 202 | int ratio_min, ratio_max, ratio_turbo, ratio_step; |
| 203 | int coord_type, power_max, power_unit, num_entries; |
| 204 | int ratio, power, clock, clock_max; |
| 205 | msr_t msr; |
| 206 | |
| 207 | /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ |
| 208 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 209 | if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) |
| 210 | coord_type = SW_ANY; |
| 211 | else |
| 212 | coord_type = HW_ALL; |
| 213 | |
| 214 | /* Get bus ratio limits and calculate clock speeds */ |
| 215 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 216 | ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ |
| 217 | |
| 218 | /* Determine if this CPU has configurable TDP */ |
| 219 | if (cpu_config_tdp_levels()) { |
| 220 | /* Set max ratio to nominal TDP ratio */ |
| 221 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 222 | ratio_max = msr.lo & 0xff; |
| 223 | } else { |
| 224 | /* Max Non-Turbo Ratio */ |
| 225 | ratio_max = (msr.lo >> 8) & 0xff; |
| 226 | } |
| 227 | clock_max = ratio_max * HASWELL_BCLK; |
| 228 | |
| 229 | /* Calculate CPU TDP in mW */ |
| 230 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 231 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 232 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 233 | power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; |
| 234 | |
| 235 | /* Write _PCT indicating use of FFixedHW */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 236 | acpigen_write_empty_PCT(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 237 | |
| 238 | /* Write _PPC with no limit on supported P-state */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 239 | acpigen_write_PPC_NVS(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 240 | |
| 241 | /* Write PSD indicating configured coordination type */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 242 | acpigen_write_PSD_package(core, 1, coord_type); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 243 | |
| 244 | /* Add P-state entries in _PSS table */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 245 | acpigen_write_name("_PSS"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 246 | |
| 247 | /* Determine ratio points */ |
| 248 | ratio_step = PSS_RATIO_STEP; |
| 249 | num_entries = (ratio_max - ratio_min) / ratio_step; |
| 250 | while (num_entries > PSS_MAX_ENTRIES-1) { |
| 251 | ratio_step <<= 1; |
| 252 | num_entries >>= 1; |
| 253 | } |
| 254 | |
| 255 | /* P[T] is Turbo state if enabled */ |
| 256 | if (get_turbo_state() == TURBO_ENABLED) { |
| 257 | /* _PSS package count including Turbo */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 258 | acpigen_write_package(num_entries + 2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 259 | |
| 260 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 261 | ratio_turbo = msr.lo & 0xff; |
| 262 | |
| 263 | /* Add entry for Turbo ratio */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 264 | acpigen_write_PSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 265 | clock_max + 1, /*MHz*/ |
| 266 | power_max, /*mW*/ |
| 267 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 268 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 269 | ratio_turbo << 8, /*control*/ |
| 270 | ratio_turbo << 8); /*status*/ |
| 271 | } else { |
| 272 | /* _PSS package count without Turbo */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 273 | acpigen_write_package(num_entries + 1); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 274 | } |
| 275 | |
| 276 | /* First regular entry is max non-turbo ratio */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 277 | acpigen_write_PSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 278 | clock_max, /*MHz*/ |
| 279 | power_max, /*mW*/ |
| 280 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 281 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 282 | ratio_max << 8, /*control*/ |
| 283 | ratio_max << 8); /*status*/ |
| 284 | |
| 285 | /* Generate the remaining entries */ |
| 286 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 287 | ratio >= ratio_min; ratio -= ratio_step) { |
| 288 | |
| 289 | /* Calculate power at this ratio */ |
| 290 | power = calculate_power(power_max, ratio_max, ratio); |
| 291 | clock = ratio * HASWELL_BCLK; |
| 292 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 293 | acpigen_write_PSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 294 | clock, /*MHz*/ |
| 295 | power, /*mW*/ |
| 296 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 297 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 298 | ratio << 8, /*control*/ |
| 299 | ratio << 8); /*status*/ |
| 300 | } |
| 301 | |
| 302 | /* Fix package length */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 303 | acpigen_pop_len(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 304 | } |
| 305 | |
Alexander Couzens | 5eea458 | 2015-04-12 22:18:55 +0200 | [diff] [blame] | 306 | void generate_cpu_entries(device_t device) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 307 | { |
Duncan Laurie | 1ad5564 | 2013-03-07 14:08:04 -0800 | [diff] [blame] | 308 | int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 309 | int totalcores = dev_count_cpu(); |
| 310 | int cores_per_package = get_cores_per_package(); |
| 311 | int numcpus = totalcores/cores_per_package; |
| 312 | |
| 313 | printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", |
| 314 | numcpus, cores_per_package); |
| 315 | |
Martin Roth | 9944b28 | 2014-08-11 11:24:55 -0600 | [diff] [blame] | 316 | for (cpuID = 1; cpuID <= numcpus; cpuID++) { |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame^] | 317 | for (coreID = 1; coreID <= cores_per_package; coreID++) { |
| 318 | if (coreID > 1) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 319 | pcontrol_blk = 0; |
| 320 | plen = 0; |
| 321 | } |
| 322 | |
| 323 | /* Generate processor \_PR.CPUx */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 324 | acpigen_write_processor( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 325 | (cpuID-1)*cores_per_package+coreID-1, |
| 326 | pcontrol_blk, plen); |
| 327 | |
| 328 | /* Generate P-state tables */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 329 | generate_P_state_entries( |
Duncan Laurie | 25b8b7b | 2013-04-19 10:02:23 -0700 | [diff] [blame] | 330 | coreID-1, cores_per_package); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 331 | |
| 332 | /* Generate C-state tables */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 333 | generate_C_state_entries(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 334 | |
| 335 | /* Generate T-state tables */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 336 | generate_T_state_entries( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 337 | cpuID-1, cores_per_package); |
| 338 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 339 | acpigen_pop_len(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 340 | } |
| 341 | } |
| 342 | } |
| 343 | |
| 344 | struct chip_operations cpu_intel_haswell_ops = { |
| 345 | CHIP_NAME("Intel Haswell CPU") |
| 346 | }; |