blob: f4e730ce9083e88945cb4a2f66f8318f2c8b4622 [file] [log] [blame]
Thaminda Edirisooriya8fad21d2015-07-29 17:43:20 -07001##
2## This file is part of the coreboot project.
3##
Thaminda Edirisooriya8fad21d2015-07-29 17:43:20 -07004##
Patrick Georgi8dd1b212020-05-08 23:13:39 +02005## SPDX-License-Identifier: GPL-2.0-only
Thaminda Edirisooriya8fad21d2015-07-29 17:43:20 -07006
Jonathan Neuschäfer5fba1ea2018-10-06 00:04:33 +02007if BOARD_EMULATION_SPIKE_RISCV
Thaminda Edirisooriya8fad21d2015-07-29 17:43:20 -07008
Elyes HAOUASf0c5be22018-11-27 20:36:44 +01009config BOARD_SPECIFIC_OPTIONS
Thaminda Edirisooriya8fad21d2015-07-29 17:43:20 -070010 def_bool y
Philipp Hugb09e5002019-02-06 06:48:51 +010011 select ARCH_RISCV_RV64
Thaminda Edirisooriya8fad21d2015-07-29 17:43:20 -070012 select SOC_UCB_RISCV
13 select BOARD_ROMSIZE_KB_4096
Jonathan Neuschäferd15e9aa2016-06-10 19:35:16 +020014 select DRIVERS_UART_8250MEM
Aaron Durbin4a36c4e2016-08-11 11:02:26 -050015 select BOOT_DEVICE_NOT_SPI_FLASH
Nico Huber9df62b02018-10-17 19:40:26 +020016 select MISSING_BOARD_RESET
Thaminda Edirisooriya8fad21d2015-07-29 17:43:20 -070017
18config MAINBOARD_DIR
19 string
Patrick Georgi0bb83462019-11-22 20:58:58 +010020 default "emulation/spike-riscv"
Thaminda Edirisooriya8fad21d2015-07-29 17:43:20 -070021
22config MAINBOARD_PART_NUMBER
23 string
24 default "SPIKE RISCV"
25
26config MAX_CPUS
27 int
28 default 1
29
Jonathan Neuschäfer5fba1ea2018-10-06 00:04:33 +020030endif # BOARD_EMULATION_SPIKE_RISCV