| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## |
| ## SPDX-License-Identifier: GPL-2.0-only |
| |
| if BOARD_EMULATION_SPIKE_RISCV |
| |
| config BOARD_SPECIFIC_OPTIONS |
| def_bool y |
| select ARCH_RISCV_RV64 |
| select SOC_UCB_RISCV |
| select BOARD_ROMSIZE_KB_4096 |
| select DRIVERS_UART_8250MEM |
| select BOOT_DEVICE_NOT_SPI_FLASH |
| select MISSING_BOARD_RESET |
| |
| config MAINBOARD_DIR |
| string |
| default "emulation/spike-riscv" |
| |
| config MAINBOARD_PART_NUMBER |
| string |
| default "SPIKE RISCV" |
| |
| config MAX_CPUS |
| int |
| default 1 |
| |
| endif # BOARD_EMULATION_SPIKE_RISCV |